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1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel® Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel® Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
6.1. Adding NoC Connectivity and Address Mapping to the Simulation Netlist
6.2. Generating a Simulation Registration Include File ( Intel® Quartus® Prime Compilation Flow)
6.3. Generating a Simulation Registration Include File (Optional Early RTL Simulation Flow)
6.4. Contents of Simulation Registration Include File
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4 Lite Interfaces
8.1.2.2. NoC Initiator AXI4 User Interface Signals
8.1.2.3. NoC Initiator Intel FPGA IP AXI4 Lite User Interface Signals
8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals
8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
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4.1. Hard Memory NoC Design Flow Overview
Creating a hard memory NoC design in the Intel® Quartus® Prime software consists of the following high level steps that this chapter describes in detail:
Figure 15. Hard Memory NoC Design Flow
- Instantiate NoC-related IP, including the NoC Initiator Intel FPGA IP, the HBM2E IP or external memory IP that contain the NoC targets, and the NoC Clock Control Intel FPGA IP in your design using Platform Designer or directly in design RTL.
Note: If you enter NoC connectivity and addressing in Platform Designer, you can use an optional early simulation flow, as Options for Specifying NoC Connectivity and Addressing describes.
- Run Intel® Quartus® Prime Analysis & Elaboration (Processing > Start > Start Analysis & Elaboration).
- Define logical constraints for NoC connectivity, addressing, and performance targets in the NoC Assignment Editor, as Making NoC Logical Assignments describes.
Note: If you define NoC connectivity and addressing in Platform Designer, you must also define the same exact NoC groups, connectivity, and addressing in the NoC Assignment Editor before Intel® Quartus® Prime compilation.
- (Optional) Rerun Analysis & Elaboration and perform RTL simulation of the NoC design, as Simulating NoC Designs describes.
- (Recommended) Run Analysis & Synthesis and then assign physical locations for NoC elements and other periphery elements, as Step 5: Make Physical Assignments Using Interface Planner describes. Otherwise, the Intel® Quartus® Prime Fitter makes the physical assignments during design compilation.
- Compile your design and review the placement and performance reports, as Compiling the NoC Design describes.