AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel Agilex® 7 FPGA Development Board

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Date 2/14/2024
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Answers to Top FAQs AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board x
Partial Reconfiguration External Configuration Controller Intel FPGA IP Reference Design Requirements Reference Design Walkthrough Hardware Testing Flow Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Answers to Top FAQs
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board

Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP

The Partial Reconfiguration External Configuration Controller Intel FPGA IP interfaces with the Intel Agilex PR control block to manage the bitstream source. You must add this IP to your design to implement external configuration.

Follow these steps to add the Partial Reconfiguration External Configuration Controller Intel FPGA IP to your project:

  1. Type Partial Reconfiguration in the IP Catalog search field (Tools > IP Catalog).
  2. Double-click Partial Reconfiguration External Configuration Controller Intel FPGA IP.
  3. In the Create IP Variant dialog box, type external_host_pr_ip as the File name, and then click Create. The parameter editor appears.
  4. For the Enable busy interface parameter, select Disable (the default setting). When you need to use this signal, you can switch the setting to Enable.
    Figure 6. Enable Busy Interface Parameter in Parameter Editor


  5. Click File > Save and exit the parameter editor without generating the system. The parameter editor generates the external_host_pr_ip.ip IP variation file and adds the file to the blinking_led project.
    Note:
    1. If you are copying the external_host_pr_ip.ip file from the pr directory, manually edit the blinking_led.qsf file to include the following line:
      set_global_assignment -name IP_FILE pr_ip.ip
    2. Place the IP_FILE assignment after the SDC_FILE assignments (blinking_led.sdc) in your blinking_led.qsf file. This ordering ensures appropriate constraining of the Partial Reconfiguration Controller IP core.
Note: To detect the clocks, the .sdc file for the PR IP must follow any .sdc that creates the clocks that the IP core uses. You facilitate this order by ensuring that the .ip file for the PR IP core appears after any .ip files or .sdc files that you use to define these clocks in the .qsf file for your Intel Quartus Prime project revision. For more information, refer to the Partial Reconfiguration IP Solutions User Guide.

Section Content
Updating the Top-Level Design

Level Two Title