AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design: for Intel Agilex® 7 FPGA Development Board

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Date 2/14/2024
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Answers to Top FAQs AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board x
Partial Reconfiguration External Configuration Controller Intel FPGA IP Reference Design Requirements Reference Design Walkthrough Hardware Testing Flow Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Answers to Top FAQs
AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board

Step 3: Allocating Placement and Routing Region for a PR Partition

For every base revision you create, the PR design flow places the corresponding persona core in your PR partition region. To locate and assign the PR region in the device floorplan for your base revision:
  1. Right-click the u_blinking_led instance in the Project Navigator and click Logic Lock Region > Create New Logic Lock Region. The region appears in the Logic Lock Regions Window.
  2. Edit the Logic Lock Region name in the Logic Lock Regions Window by double-clicking the name. For this reference design, rename the Logic Lock Region to pr_partition.
  3. In the Logic Lock Regions window, specify the placement region co-ordinates in the Origin column. The origin corresponds to the lower-left corner of the region. For example, to set a placement region with (X1 Y1) co-ordinates as (163 4), specify the Origin as X163_Y4. The Intel® Quartus® Prime software automatically calculates the (X2 Y2) co-ordinates (top-right) for the placement region, based on the height and width you specify.
    Note: This tutorial uses the (X1 Y1) co-ordinates - (163 4), and a height and width of 20 for the placement region. Define any value for the placement region. Ensure that the region covers the blinking_led logic.
  4. Enable the Reserved and Core-Only options.
  5. Double-click the Routing Region option. The Logic Lock Routing Region Settings dialog box appears.
  6. Select Fixed with expansion for the Routing type. Selecting this option automatically assigns an expansion length of 2.
    Note: The routing region must be larger than the placement region, to provide extra flexibility for the Fitter when the engine routes different personas.
    Figure 4.  Logic Lock Regions Window


  7. Your placement region must enclose the blinking_led logic. Select the placement region by locating the node in Chip Planner. Right-click the pr_partition region name in the Logic Lock Regions Window and click Locate Node > Locate in Chip Planner.

    The pr_partition region is color-coded.

    Figure 5. Chip Planner Node Location


Verify that the blinking_led.qsf contains the following assignments, corresponding to your floorplanning: 
set_instance_assignment -name PLACE_REGION "X163 Y4 X182 Y23" -to \
        u_blinking_led 
set_instance_assignment -name RESERVE_PLACE_REGION ON -to \
        u_blinking_led
set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to \
        u_blinking_led
set_instance_assignment -name ROUTE_REGION "X161 Y2 X184 Y25" -to \
        u_blinking_led
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