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Partial Reconfiguration External Configuration Controller Intel FPGA IP
Reference Design Requirements
Reference Design Walkthrough
Hardware Testing Flow
Document Revision History for AN 991: Partial Reconfiguration via Configuration Pins (External Host) Reference Design for Intel Agilex® 7 FPGA Development Board
Step 1: Getting Started
Step 2: Creating a Design Partition
Step 3: Allocating Placement and Routing Region for a PR Partition
Step 4: Adding the Partial Reconfiguration External Configuration Controller Intel FPGA IP
Step 5: Defining Personas
Step 6: Creating Revisions
Step 7: Compiling the Base Revision
Step 8: Preparing PR Implementation Revisions
Step 9: Programming the Board
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Updating the Top-Level Design
To update the top.sv file with the PR_IP instance:
- To add the external_host_pr_ip instance to the top-level design, uncomment the following code blocks in the top.sv file:
///////////////////////////////////////////////////////// // Status signals from external PR IP /////////////////////////////////////////////////////////// input wire pr_request, output_wire pr_done, output_wire [1:0] pr_error
wire clock_out;
external_host_pr_ip u_pr_ip .outclk (clock_out), .reset (1'b0), .pr_request (pr_request), .pr_done (pr_done), .pr_error (pr_error) );
- Save the file.