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Ixiasoft
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Generating Tile Files
1.4. Simulating the F-tile 25G Ethernet Intel FPGA IP Design Example Testbench
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
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Ixiasoft
2.4.1. Testbench
Figure 6. Block Diagram of the F-tile 25G Ethernet Intel FPGA IP Design Example Simulation Testbench
Component | Description |
---|---|
Device under test (DUT) | The 25G Ethernet Intel FPGA IP core. |
Ethernet Packet Generator and Packet Monitor |
|
F-Tile Reference and System PLL Clocks Intel® FPGA IP | Generates transceiver and system PLL reference clocks. |