F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

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ID 750200
Date 10/14/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-tile 25G Ethernet Design Example for Intel® Agilex™ Devices 3. Document Revision History for F-tile 25G Ethernet FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Generating Tile Files 1.4. Simulating the F-tile 25G Ethernet Intel FPGA IP Design Example Testbench 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-tile 25G Ethernet Intel FPGA IP Hardware Design Example
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-tile 25G Ethernet Design Example for Intel® Agilex™ Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
1. Quick Start Guide
2. F-tile 25G Ethernet Design Example for Intel® Agilex™ Devices
3. Document Revision History for F-tile 25G Ethernet FPGA IP Design Example User Guide

2.3.1. Design Components

Table 4.  Design Components
Component Description
F-tile 25G Ethernet Intel FPGA IP

Consists of MAC, PCS, and Transceiver PHY, with the following configuration:

  • Core Variant: MAC+PCS+PMA
  • Enable flow control: Optional
  • Enable link fault generation: Optional
  • Enable preamble passthrough: Optional
  • Enable statistics collection: Optional
  • Enable MAC statistics counters: Optional
  • Reference clock frequency: 156.25
For the design example with the RS-FEC feature, the following additional parameter is configured:
  • Enable RS-FEC: Optional
F-Tile Reference and System PLL Clocks Intel® FPGA IP

The F-Tile Reference and System PLL Clocks Intel® FPGA IP parameter editor settings align with the requirements of the F-tile 25G Ethernet Intel FPGA IP. If you generate the design example using Generate Example Design button in the IP parameter editor, the IP instantiates automatically. If you create your own design example, you must manually instantiate this IP and connect all I/O ports.

For information about this IP, refer to F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.

Client logic Consists of:
  • Traffic generator, which generates burst packets to the 25G Ethernet Intel FPGA IP core for transmission.
  • Traffic monitor, which monitors burst packets that are coming from the 25G Ethernet Intel FPGA IP core.
Source and Probe Source and probe signals, including system reset input signal, which you can use for debugging.
Related Information
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