Visible to Intel only — GUID: fja1652190426529
Ixiasoft
Visible to Intel only — GUID: fja1652190426529
Ixiasoft
12.6. Nios® V Processor Design Example Scripts
You can generate a Nios® V processor design example from the IP Parameter Editor in Platform Designer. By selecting the desired design example, a zip file is downloaded into your desired directory.
The design examples provide scripts that allow you to automate the design example generation, and build both a BSP project and a simple application project. The design examples are preset to an Intel FPGA device. If you targeting a different Intel FPGA device, please perform device migration to the design example project.
- New device assignment
- Go to Assignments > Device...
- Select the appropriate Device family and Name.
Note: If SmartVID feature is supported, please configure the correct SmartVID settings.
- New pin assignment
- Go to Assignments > Editor.
- Reassign the appropriate pin assignment to the board.
- Recompile the design example.
File | Descriptions |
---|---|
readme.txt | Describe the design example details and provide steps to run the design example automation scripts |
create_design.py | The primary python script that calls out others automation Tcl script to build the design example |
toggle_issp.tcl | Tcl script to reset the design via ISSP |
Build Flow from readme.txt (GSFI Bootloader Example Design)
#Launch niosv-shell
<ACDS>/niosv/niosv-shell
#Run create_design.py to build the example design and program the board
quartus_py create_design.py
#Reset the design via ISSP (quartus_stp)
quartus_stp -t toggle_issp.tcl
#Run terminal to view stdout / stderr of Nios V application (juart-terminal):
juart-terminal