Nios® V Processor Software Developer Handbook

ID 743810
Date 10/31/2022
Public

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12.6. Nios® V Processor Design Example Scripts

You can generate a Nios® V processor design example from the IP Parameter Editor in Platform Designer. By selecting the desired design example, a zip file is downloaded into your desired directory.

The design examples provide scripts that allow you to automate the design example generation, and build both a BSP project and a simple application project. The design examples are preset to an Intel FPGA device. If you targeting a different Intel FPGA device, please perform device migration to the design example project.

The following are the basic device migration steps:
  1. New device assignment
    1. Go to Assignments > Device...
    2. Select the appropriate Device family and Name.
      Note: If SmartVID feature is supported, please configure the correct SmartVID settings.
  2. New pin assignment
    1. Go to Assignments > Editor.
    2. Reassign the appropriate pin assignment to the board.
  3. Recompile the design example.
Figure 20. IP Parameter Editor for Nios® V/m Processor Intel FPGA IP
Figure 21. Select Example Design Directory
Note: The script may vary from other design example. Please utilize the design example readme.txt for detail flow to generate and run the design example
Table 50.  Example Script Files (GSFI Bootloader Example Design)
File Descriptions
readme.txt Describe the design example details and provide steps to run the design example automation scripts
create_design.py The primary python script that calls out others automation Tcl script to build the design example
toggle_issp.tcl Tcl script to reset the design via ISSP

Build Flow from readme.txt (GSFI Bootloader Example Design)

#Launch niosv-shell
<ACDS>/niosv/niosv-shell

#Run create_design.py to build the example design and program the board
quartus_py create_design.py

#Reset the design via ISSP (quartus_stp)
quartus_stp -t toggle_issp.tcl

#Run terminal to view stdout / stderr of Nios V application (juart-terminal):
juart-terminal