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1. Overview of Nios® V Embedded Processor Development
2. Getting Started from the Command Line
3. Nios® V Processor Software Development and Implementation
4. Nios® V Processor Board Support Package Editor
5. Overview of the Hardware Abstraction Layer
6. Developing Programs Using the Hardware Abstraction Layer
7. Developing Device Drivers for the Hardware Abstraction Layer
8. Exception Handling
9. MicroC/OS-II Real-Time Operating System
10. MicroC/TCP-IP Protocol Stack
11. Publishing Component Information to Embedded Software
12. Nios® V Processor Appendix
A. Nios® V Processor Software Developer Handbook Archives
13. Revision History for Nios® V Processor Software Developer Handbook
6.1. HAL BSP Settings
6.2. The Nios® V Processor Embedded Project Structure
6.3. The system.h System Description File
6.4. Data Widths and the HAL Type Definitions
6.5. UNIX-Style Interface
6.6. Using Character-Mode Devices
6.7. Using Timer Devices
6.8. Using Flash Devices
6.9. Using DMA Devices
6.10. Interrupt Controllers
6.11. Reducing Code Footprint in Embedded Systems
6.12. Boot Sequence and Entry Point
6.13. Memory Usage
6.14. Working with HAL Source Files
7.1. Driver Integration in the HAL API
7.2. The HAL Peripheral-Specific API
7.3. Preparing for HAL Driver Development
7.4. Development Flow for Creating Device Drivers
7.5. Nios® V Processor Hardware Design Concepts
7.6. Accessing Hardware
7.7. Creating Embedded Drivers for HAL Device Classes
7.8. Integrating a Device Driver in the HAL
7.9. Creating a Custom Device Driver for the HAL
7.10. Reducing Code Footprint in HAL Embedded Drivers
7.11. HAL Namespace Allocation
7.12. Overriding the HAL Default Device Drivers
7.8.5.2.1. Creating and Naming the Driver or Package
7.8.5.2.2. Identifying the Hardware Component Class
7.8.5.2.3. Setting the BSP Type
7.8.5.2.4. Specifying an Operating System
7.8.5.2.5. Specifying Source Files
7.8.5.2.6. Specifying a Subdirectory
7.8.5.2.7. Enabling Software Initialization
7.8.5.2.8. Adding Include Paths
7.8.5.2.9. Version Compatibility
8.1. Nios® V Processor Exception Handling Overview
8.2. Nios® V Processor Hardware Interrupt Service Routines
8.3. Nios® V Processor Software Interrupt Service Routines
8.4. Improving Nios® V Processor ISR Performance
8.5. Debugging Nios® V Processor ISRs
8.6. HAL Exception Handling System Implementation
8.7. Nios® V Processor Instruction-Related Exception Handler
8.4.1.1. Execute Time-Intensive Algorithms in the Application Context
8.4.1.2. Implement Time-Intensive Algorithms in Hardware
8.4.1.3. Increase Buffer Size
8.4.1.4. Use Double Buffering
8.4.1.5. Keep Interrupts Enabled
8.4.1.6. Use Fast Memory
8.4.1.7. Use a Separate Exception Stack
8.4.1.8. Use Nested Hardware Interrupts
8.4.1.9. Use Compiler Optimization
10.1. Overview of the MicroC/TCP-IP Protocol Stack
10.2. Support and Licensing
10.3. Prerequisites for Understanding the MicroC/TCP-IP Protocol Stack
10.4. Introduction to the MicroC/TCP-IP Protocol Stack - Nios® V Processor Edition
10.5. The MicroC/TCP-IP Protocol Stack Files and Directories
10.6. Enabling MicroC/TCP-IP Protocol Stack
10.7. Using the MicroC/TCP-IP Protocol Stack
12.1.1.1. _exit()
12.1.1.2. _rename()
12.1.1.3. alt_dcache_flush()
12.1.1.4. alt_dcache_flush_all()
12.1.1.5. alt_icache_flush_all()
12.1.1.6. alt_dcache_flush_no_writeback()
12.1.1.7. alt_uncached_malloc()
12.1.1.8. alt_uncached_free()
12.1.1.9. alt_remap_uncached()
12.1.1.10. alt_remap_cached()
12.1.1.11. alt_icache_flush_all()
12.1.1.12. alt_icache_flush()
12.1.1.13. alt_alarm_start()
12.1.1.14. alt_alarm_stop()
12.1.1.15. alt_dma_rxchan_depth()
12.1.1.16. alt_dma_rxchan_close()
12.1.1.17. alt_dev_reg()
12.1.1.18. alt_dma_rxchan_open()
12.1.1.19. alt_dma_rxchan_prepare()
12.1.1.20. alt_dma_rxchan_reg()
12.1.1.21. alt_dma_txchan_close()
12.1.1.22. alt_dma_txchan_ioctl()
12.1.1.23. alt_dma_txchan_open()
12.1.1.24. alt_dma_txchan_reg()
12.1.1.25. alt_flash_close_dev()
12.1.1.26. alt_exception_cause_generated_bad_addr()
12.1.1.27. alt_erase_flash_block()
12.1.1.28. alt_dma_rxchan_ioctl()
12.1.1.29. alt_dma_txchan_space()
12.1.1.30. alt_dma_txchan_send()
12.1.1.31. alt_flash_open_dev()
12.1.1.32. alt_fs_reg()
12.1.1.33. alt_get_flash_info()
12.1.1.34. alt_ic_irq_disable()
12.1.1.35. alt_ic_irq_enabled()
12.1.1.36. alt_ic_isr_register()
12.1.1.37. alt_ic_irq_enable()
12.1.1.38. alt_instruction_exception_register()
12.1.1.39. alt_irq_cpu_enable_interrupts ()
12.1.1.40. alt_irq_disable_all()
12.1.1.41. alt_irq_enable_all()
12.1.1.42. alt_irq_enabled()
12.1.1.43. alt_irq_init()
12.1.1.44. alt_irq_pending ()
12.1.1.45. alt_llist_insert()
12.1.1.46. alt_llist_remove()
12.1.1.47. alt_load_section()
12.1.1.48. alt_nticks()
12.1.1.49. alt_read_flash()
12.1.1.50. alt_tick()
12.1.1.51. alt_ticks_per_second()
12.1.1.52. alt_timestamp()
12.1.1.53. alt_timestamp_freq()
12.1.1.54. alt_timestamp_start()
12.1.1.55. alt_write_flash()
12.1.1.56. alt_write_flash_block()
12.1.1.57. close()
12.1.1.58. fstat()
12.1.1.59. fork()
12.1.1.60. fcntl()
12.1.1.61. execve()
12.1.1.62. getpid()
12.1.1.63. kill()
12.1.1.64. stat()
12.1.1.65. settimeofday()
12.1.1.66. wait()
12.1.1.67. unlink()
12.1.1.68. sbrk()
12.1.1.69. link()
12.1.1.70. lseek()
12.1.1.71. open()
12.1.1.72. alt_sysclk_init()
12.1.1.73. times()
12.1.1.74. read()
12.1.1.75. write()
12.1.1.76. usleep()
12.1.1.77. alt_lock_flash()
12.1.1.78. gettimeofday()
12.1.1.79. ioctl()
12.1.1.80. isatty()
12.1.1.81. alt_niosv_enable_msw_interrupt()
12.1.1.82. alt_niosv_disable_msw_interrupt()
12.1.1.83. alt_niosv_is_msw_interrupt_enabled()
12.1.1.84. alt_niosv_trigger_msw_interrupt()
12.1.1.85. alt_niosv_clear_msw_interrupt()
12.1.1.86. alt_niosv_register_msw_interrupt_handler()
12.5.2.1. add_memory_device
12.5.2.2. add_memory_region
12.5.2.3. add_section_mapping
12.5.2.4. are_same_resource
12.5.2.5. delete_memory_region
12.5.2.6. delete_section_mapping
12.5.2.7. disable_sw_package
12.5.2.8. enable_sw_package
12.5.2.9. get_addr_span
12.5.2.10. get_assignment
12.5.2.11. get_available_drivers
12.5.2.12. get_available_sw_packages
12.5.2.13. get_base_addr
12.5.2.14. get_break_offset
12.5.2.15. get_break_slave_desc
12.5.2.16. get_cpu_name
12.5.2.17. get_current_memory_regions
12.5.2.18. get_current_section_mappings
12.5.2.19. get_default_memory_regions
12.5.2.20. get_driver
12.5.2.21. get_enabled_sw_packages
12.5.2.22. get_exception_offset
12.5.2.23. get_exception_slave_desc
12.5.2.24. get_fast_tlb_miss_exception_offset
12.5.2.25. get_fast_tlb_miss_exception_slave_desc
12.5.2.26. get_interrupt_controller_id
12.5.2.27. get_irq_interrupt_controller_id
12.5.2.28. get_irq_number
12.5.2.29. get_memory_region
12.5.2.30. get_module_class_name
12.5.2.31. get_module_name
12.5.2.32. get_reset_offset
12.5.2.33. get_reset_slave_desc
12.5.2.34. get_section_mapping
12.5.2.35. get_setting
12.5.2.36. get_setting_desc
12.5.2.37. get_slave_descs
12.5.2.38. is_char_device
12.5.2.39. is_connected_interrupt_controller_device
12.5.2.40. is_connected_to_data_master
12.5.2.41. is_connected_to_instruction_master
12.5.2.42. is_ethernet_mac_device
12.5.2.43. is_flash
12.5.2.44. is_memory_device
12.5.2.45. is_non_volatile_storage
12.5.2.46. is_timer_device
12.5.2.47. log_debug
12.5.2.48. log_default
12.5.2.49. log_error
12.5.2.50. log_verbose
12.5.2.51. set_driver
12.5.2.52. set_ignore_file
12.5.2.53. set_setting
12.5.2.54. update_memory_region
12.5.2.55. update_section_mapping
12.5.2.56. add_default_memory_regions
12.5.2.57. create_bsp
12.5.2.58. generate_bsp
12.5.2.59. get_available_bsp_type_versions
12.5.2.60. get_available_bsp_types
12.5.2.61. get_available_cpu_architectures
12.5.2.62. get_available_cpu_names
12.5.2.63. get_available_software
12.5.2.64. get_available_software_setting_properties
12.5.2.65. get_available_software_settings
12.5.2.66. get_bsp_version
12.5.2.67. get_cpu_architecture
12.5.2.68. get_sopcinfo_file
12.5.2.69. get_supported_bsp_types
12.5.2.70. is_bsp_hal_extension
12.5.2.71. open_bsp
12.5.2.72. save_bsp
12.5.2.73. set_bsp_version
12.5.2.74. set_logging_mode
12.5.3.1. add_class_sw_setting
12.5.3.2. add_class_systemh_line
12.5.3.3. add_module_sw_property
12.5.3.4. add_module_sw_setting
12.5.3.5. add_module_systemh_line
12.5.3.6. add_systemh_line
12.5.3.7. get_class_peripheral
12.5.3.8. get_module_assignment
12.5.3.9. get_module_name
12.5.3.10. get_module_peripheral
12.5.3.11. get_module_sw_setting_value
12.5.3.12. get_peripheral_property
12.5.3.13. remove_class_systemh_line
12.5.3.14. remove_module_systemh_line
12.5.3.15. set_class_sw_setting_property
12.5.3.16. set_module_sw_setting_property
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11.2.2.3. Memory-Mapped Slave Information
Configuration Name | Type | Default | Meaning | Examples |
---|---|---|---|---|
isMemoryDevice | boolean | 0 | The slave port provides access to a memory device. | Intel® FPGA® On-Chip Memory Component, DDR Controller,Quad Serial Peripheral Interface (QSPI) flash device controller |
isPrintableDevice | boolean | 0 | The slave port provides access to a character-based device. | Intel® FPGA UART, Intel FPGA JTAG UART |
isTimerDevice | boolean | 0 | The slave port provides access to a timer device. | Intel® FPGA Timer |
isEthernetMacDevice | boolean | 0 | The slave port provides access to an Ethernet media access control (MAC). | Intel® FPGA Triple-Speed Ethernet |
isNonVolatileStorage | boolean | 0 | The memory device is a non-volatile memory device. The contents of a non-volatile memory device are fixed and always present. In normal operation, you can only read from this memory. If this property is true, you must also set isMemoryDevice to true. | QSPI flash devices, on-chip FPGA memory configured as a ROM |
isFlash | boolean | 0 | The memory device is a flash memory device. If isFlash is true, you must also set isMemoryDevice and isNonVolatileStorage to true. | QSPI flash devices |
affectsTransactionsOnMasters | string | empty string |
A list of master names delimited by spaces, for example m1 m2. Used when the slave port provides access to Avalon-MM control registers in the component. The control registers control transfers on the specified master ports. The slave port can configure the control registers for master ports on the listed components. The address space for this slave port is composed of the address spaces of the named master ports. Nios® V embedded software tools use this information to generate #define directives describing the address space of these master ports. |
Intel® FPGA direct memory access (DMA), Modular Scatter-Gather DMA |