Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

Download PDF
ID 730783
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Installation and Setup 3. Getting Started with RiscFree* IDE 4. Debug Setup for Nios® V Processor System 5. Debug Setup for Arm* Hard Processor System 6. Debugging with RiscFree* IDE 7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices
2. Installation and Setup x
2.1. Bundled Installation with the Intel® Quartus® Prime Software 2.2. Standalone Installation
2.2. Standalone Installation x
2.2.1. Standalone Installation with Supported Intel® Quartus® Prime Software 2.2.2. Standalone Installation with the Intel® Quartus® Prime Pro Edition Programmer and Tools
3. Getting Started with RiscFree* IDE x
3.1. Graphical User Interface 3.2. Command Line Interface
4. Debug Setup for Nios® V Processor System x
4.1. Importing Nios® V Project 4.2. Building Nios® V Project 4.3. Setting Debug Configurations and Downloading Nios® V Project Using RiscFree* IDE
5. Debug Setup for Arm* Hard Processor System x
5.1. Pre-requisite for Debugging Arm* HPS Project 5.2. Importing Arm* HPS Project 5.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
6. Debugging with RiscFree* IDE x
6.1. Debug Features in RiscFree* IDE 6.2. Processor System Debug 6.3. Heterogeneous Multicore Debug 6.4. Debugging µC/OS-II Application
6.1. Debug Features in RiscFree* IDE x
6.1.1. Viewing Global Variables 6.1.2. Launching Memory Browser 6.1.3. Debugger Console 6.1.4. Specifying the SVD File 6.1.5. Breakpoint Settings 6.1.6. JTAG UART Output Terminal
6.2. Processor System Debug x
6.2.1. GUI for Debugging
6.3. Heterogeneous Multicore Debug x
6.3.1. Importing Nios® V and Arm* HPS Projects 6.3.2. Setting Core Configuration
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Installation and Setup
3. Getting Started with RiscFree* IDE
4. Debug Setup for Nios® V Processor System
5. Debug Setup for Arm* Hard Processor System
6. Debugging with RiscFree* IDE
7. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
8. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

A.2. Performing External Tools Configuration

External tool configuration is a generic feature where you can configure the RiscFree* IDE to include tools based on your requirement.

To perform external tool configuration for juart terminal, follow these steps:

  1. Go to Run > External Tools > External Tools Configurations…. Double click Program to open a New_configuration window.
  2. Rename the configuration as Nios V JTAG UART Output.
  3. Browse and select the juart-terminal file in the following paths:
    Operating System Path
    Windows* Intel® Quartus® Prime Software <Intel Quartus Prime installation directory>/quartus/bin64/juart-terminal.exe
    Intel® Quartus® Prime Pro Edition Programmer and Tools <Intel Quartus Prime installation directory>/qprogrammer/quartus/bin64/juart-terminal.exe
    Linux* Intel® Quartus® Prime Software <Intel Quartus Prime installation directory>/quartus/linux64/juart-terminal
    Intel® Quartus® Prime Pro Edition Programmer and Tools <Intel Quartus Prime installation directory>/qprogrammer/quartus/linux64/juart-terminal
  4. Set the preferred arguments. In this example, set the arguments as follows:
    • Connect to JTAG UART at cable 1: -c 1
    • Connect to device 0: -d 0
    • Connect to instance 0: -i 0
    Note: JTAG device chain index varies according to your setup. To obtain the latest device chain index numbering, run openocd-cfg-gen --print command in Nios® V Command Shell.
    Figure 28. External Tools Configuration
    Note: The steps are also applicable to other Nios® V tools (niosv-app and niosv-bsp) under <Intel Quartus Prime installation directory>/niosv/bin directory. These tools are not available for standalone RiscFree* IDE installation with the Intel® Quartus® Prime Pro Edition Programmer and Tools.
Level Two Title