F-Tile Dynamic Reconfiguration Design Example User Guide

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ID 710582
Date 4/11/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for CPRI Multirate Design Example 3. Detailed Description for Ethernet Multirate Design Example 4. Detailed Description for Ethernet Multirate Design Example with Enabled Auto-Negotiation and Link Training 5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example 6. Detailed Description for Ethernet to CPRI Design Example 7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives 8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Compiling the Compilation-Only Project 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
1.2. Generating the Design x
1.2.1. CPRI Multirate Design Example Parameters 1.2.2. Ethernet Multirate Design Example Parameters 1.2.3. PMA/FEC Direct PHY Multirate Design Example Parameters 1.2.4. Ethernet to CPRI Design Example Parameters
2. Detailed Description for CPRI Multirate Design Example x
2.1. CPRI Multirate Design Example: Functional Description 2.2. CPRI Multirate Design Example: Registers
2.1. CPRI Multirate Design Example: Functional Description x
2.1.1. CPRI Multirate Design Example: Simulation Testbench 2.1.2. CPRI Multirate Hardware Design Example 2.1.3. CPRI Multirate Design Example: Reset Scheme
3. Detailed Description for Ethernet Multirate Design Example x
3.1. Ethernet Multirate Design Example: Functional Description 3.2. Ethernet Multirate Design Example: Registers
3.1. Ethernet Multirate Design Example: Functional Description x
3.1.1. Ethernet Multirate Design Example: Simulation Testbench 3.1.2. Ethernet Multirate Hardware Design Example 3.1.3. Ethernet Multirate Design Example: Reset Scheme
4. Detailed Description for Ethernet Multirate Design Example with Enabled Auto-Negotiation and Link Training x
4.1. Ethernet Multirate Design Example with Enabled AN/LT: Functional Description
4.1. Ethernet Multirate Design Example with Enabled AN/LT: Functional Description x
4.1.1. Ethernet Multirate Design Example with Enabled AN/LT: Simulation Testbench 4.1.2. Ethernet Multirate Hardware Design Example with Enabled AN/LT
4.1.2. Ethernet Multirate Hardware Design Example with Enabled AN/LT x
4.1.2.1. Ethernet Multirate Design Example with Enabled AN/LT: Reset Scheme
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example x
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description 5.2. PMA/FEC Direct PHY Multirate Design Example: Registers
5.1. PMA/FEC Direct PHY Multirate Design Example: Functional Description x
5.1.1. PMA/FEC Direct PHY Multirate Design Example: Simulation Testbench 5.1.2. PMA/FEC Direct PHY Multirate Hardware Design Example 5.1.3. PMA/FEC Direct Multirate Design Example: Reset Scheme
6. Detailed Description for Ethernet to CPRI Design Example x
6.1. Ethernet to CPRI Design Example: Functional Description 6.2. Ethernet to CPRI Design Example: Registers
6.1. Ethernet to CPRI Design Example: Functional Description x
6.1.1. Ethernet to CPRI Dynamic Reconfiguration Design Example: Simulation Testbench 6.1.2. Ethernet to CPRI Dynamic Reconfiguration Hardware Design Example 6.1.3. Ethernet to CPRI Dynamic Reconfiguration Design Example: Reset Scheme
1. Quick Start Guide
2. Detailed Description for CPRI Multirate Design Example
3. Detailed Description for Ethernet Multirate Design Example
4. Detailed Description for Ethernet Multirate Design Example with Enabled Auto-Negotiation and Link Training
5. Detailed Description for PMA/FEC Direct PHY Multirate Design Example
6. Detailed Description for Ethernet to CPRI Design Example
7. F-Tile Dynamic Reconfiguration Design Example User Guide Archives
8. Document Revision History for the F-Tile Dynamic Reconfiguration Design Example User Guide

2.1.2. CPRI Multirate Hardware Design Example

Figure 8. CPRI Multirate Hardware Design Example Block Diagram

In the hardware design example, the reset, status, and control signals from packet clients, F-Tile CPRI PHY Multirate Intel® FPGA IP, and F-Tile Dynamic Reconfiguration Suite Intel® FPGA IP in the example design are connected to In-System Sources and Probes IPs (ISSP). The hardware test scripts open service to the ISSP to read and drive the values. A JTAG host is instantiated to access the Avalon® memory-mapped interfaces.

Hardware Flow for Design Example:
  1. Enable the packet round-trip measurement.
    • Perform the deterministic latency test flow.
    • Print the deterministic latency data to det_latency.log file.
  2. Power up the CPRI PHY Multirate IP DUT based on profile 0 (24G RSFEC).
  3. Initialize the testbench variables based on power-up profile. The variables are:
    • cpri_speed: To indicate the speed of the current profile.
    • enable_rsfec: To indicate whether RS-FEC is enabled or disabled for the current profile.
    • current_dr_profile: To indicate the ID of the current profile.
  4. Perform dynamic reconfiguration.
  5. Check the testbench error flag and determine whether testbench passed or failed. This error flag is set to 1 if there is any error after dynamic reconfiguration traffic tests.
For customization, you can modify the DR_TRANSITION array variable in src or parameter file to configure test flow. Profile ID is passed into Dynamic Reconfiguration IP to configure the intended dynamic reconfiguration task.
  • DR_TRANSITION: Intended dynamic reconfiguration sequence array. The size of this array variable determines the number of dynamic reconfiguration to be performed.
For example, you want to achieve this Dynamic Reconfiguration sequence: 24G RS-FEC > 10G > 4.9G. The variables changes are: 
set DR_TRANSITION(0)   "10G"
set DR_TRANSITION(1)   " 4P9G"

The sample output for the CPRI Multirate hardware design example is shown below.

Sample output for CPRI Multirate hardware design example:

Info: Number of Channels = 1
Info: JTAG Port ID       = 1
Info: Power Up Variant   = 24G_RSFEC
Info: Start of ftile_dr_cpri_test

Info: Basic CPRI DR test

	INFO: Checking PLL lock status...
	iopll_sclk_locked 1
	INFO: IOPLL sclk is locked
	INFO: Set Reconfig Reset
	INFO: Release Reconfig Reset
Loop 0
	INFO: Set RT Counter
	INFO: Channel 0: Set TX Reset
	INFO: Channel 0 : Checking tx reset ack n status...
	INFO: TX fully in reset state 
	INFO: Channel 0: Set RX Reset
	INFO: Channel 0 : Checking rx reset ack n status...
	INFO: RX fully in reset state 
	Info: Channel: 0 Configuring ED to CPRI 10G ....
	Info: Wait for DR Ready....
	Info: Trigger DR interrupt
	Info: Wait for DR interrupt Ack....
		Info: DR Request acknowledged
	Info: Wait for DR Config to be done....
		Info: DONE Reconfigure to 10G.
	INFO: Channel 0: Configuring cpri_speed
	Info: Channel: 0 Loop: 0 De-asserting reset to CPRI 10G ....
	INFO: Channel 0: Release TX Reset
	Info: Check TX Ready Attempt: 1
	INFO: Channel 0 : Checking TX ready status...
		Info: tx_ready = 1
	INFO: Channel 0: Release RX Reset
	Info: Check RX Ready Attempt: 1
	INFO: Channel 0 : Checking RX ready status...
		Info: rx_ready = 1
	INFO: Channel 0 : Checking RX PCS ready status...
		Info: rx_pcs_ready  = 1
	Info:Info: Channel: 0 Configuring DL ....
	Info Channel: 0 sending packets in progress, waiting for checker pass ***
	Info Channel: 0 waiting for measure_valid to assert...
	INFO: Channel 0 : Checking hyperframe sync status...
	INFO: hyperframe sync asserted
	INFO: Channel 0 : Checking RT count done status...
	INFO: RT count done asserted
	Channel 0 : Read Determenistic latency counts
	Channel 0 : Get checker_pass status:
	Checker value = 1
	Checker status = Passed!

**
*****************************************

	INFO: Channel 0: Set TX Reset
	INFO: Channel 0 : Checking tx reset ack n status...
	INFO: TX fully in reset state 
	INFO: Channel 0: Set RX Reset
	INFO: Channel 0 : Checking rx reset ack n status...
	INFO: RX fully in reset state 
	Info: Channel: 0 Configuring ED to CPRI 9P8G ....
	Info: Wait for DR Ready....
	Info: Trigger DR interrupt
	Info: Wait for DR interrupt Ack....
		Info: DR Request acknowledged
	Info: Wait for DR Config to be done....
		Info: DONE Reconfigure to 9P8G.
	INFO: Channel 0: Configuring cpri_speed
	Info: Channel: 0 Loop: 0 De-asserting reset to CPRI 9P8G ....
	INFO: Channel 0: Release TX Reset
	Info: Check TX Ready Attempt: 1
	INFO: Channel 0 : Checking TX ready status...
		Info: tx_ready = 1
	INFO: Channel 0: Release RX Reset
	Info: Check RX Ready Attempt: 1
	INFO: Channel 0 : Checking RX ready status...
		Info: rx_ready = 1
	Info:Info: Channel: 0 Configuring DL ....
	Info Channel: 0 sending packets in progress, waiting for checker pass ***
	Info Channel: 0 waiting for measure_valid to assert...
	INFO: Channel 0 : Checking hyperframe sync status...
	INFO: hyperframe sync asserted
	INFO: Channel 0 : Checking RT count done status...
	INFO: RT count done asserted
	Channel 0 : Read Determenistic latency counts
	Channel 0 : Get checker_pass status:
	Checker value = 1
	Checker status = Passed!

**
*****************************************

	INFO: Channel 0: Set TX Reset
	INFO: Channel 0 : Checking tx reset ack n status...
	INFO: TX fully in reset state 
	INFO: Channel 0: Set RX Reset
	INFO: Channel 0 : Checking rx reset ack n status...
	INFO: RX fully in reset state 
	Info: Channel: 0 Configuring ED to CPRI 4P9G ....
	Info: Wait for DR Ready....
	Info: Trigger DR interrupt
	Info: Wait for DR interrupt Ack....
		Info: DR Request acknowledged
	Info: Wait for DR Config to be done....
		Info: DONE Reconfigure to 4P9G.
	INFO: Channel 0: Configuring cpri_speed
	Info: Channel: 0 Loop: 0 De-asserting reset to CPRI 4P9G ....
	INFO: Channel 0: Release TX Reset
	Info: Check TX Ready Attempt: 1
	INFO: Channel 0 : Checking TX ready status...
		Info: tx_ready = 1
	INFO: Channel 0: Release RX Reset
	Info: Check RX Ready Attempt: 1
	INFO: Channel 0 : Checking RX ready status...
		Info: rx_ready = 1
	Info:Info: Channel: 0 Configuring DL ....
	Info Channel: 0 sending packets in progress, waiting for checker pass ***
	Info Channel: 0 waiting for measure_valid to assert...
	INFO: Channel 0 : Checking hyperframe sync status...
	INFO: hyperframe sync asserted
	INFO: Channel 0 : Checking RT count done status...
	INFO: RT count done asserted
	Channel 0 : Read Determenistic latency counts
	Channel 0 : Get checker_pass status:
	Checker value = 1
	Checker status = Passed!

**
*****************************************

	INFO: Channel 0: Set TX Reset
	INFO: Channel 0 : Checking tx reset ack n status...
	INFO: TX fully in reset state 
	INFO: Channel 0: Set RX Reset
	INFO: Channel 0 : Checking rx reset ack n status...
	INFO: RX fully in reset state 
	Info: Channel: 0 Configuring ED to CPRI 2P4G ....
	Info: Wait for DR Ready....
	Info: Trigger DR interrupt
	Info: Wait for DR interrupt Ack....
		Info: DR Request acknowledged
	Info: Wait for DR Config to be done....
		Info: DONE Reconfigure to 2P4G.
	INFO: Channel 0: Configuring cpri_speed
	Info: Channel: 0 Loop: 0 De-asserting reset to CPRI 2P4G ....
	INFO: Channel 0: Release TX Reset
	Info: Check TX Ready Attempt: 1
	INFO: Channel 0 : Checking TX ready status...
		Info: tx_ready = 1
	INFO: Channel 0: Release RX Reset
	Info: Check RX Ready Attempt: 1
	INFO: Channel 0 : Checking RX ready status...
		Info: rx_ready = 1
	Info:Info: Channel: 0 Configuring DL ....
	Info Channel: 0 sending packets in progress, waiting for checker pass ***
	Info Channel: 0 waiting for measure_valid to assert...
	INFO: Channel 0 : Checking hyperframe sync status...
	INFO: hyperframe sync asserted
	INFO: Channel 0 : Checking RT count done status...
	INFO: RT count done asserted
	Channel 0 : Read Determenistic latency counts
	Channel 0 : Get checker_pass status:
	Checker value = 1
	Checker status = Passed!

**
*****************************************

	INFO: Channel 0: Set TX Reset
	INFO: Channel 0 : Checking tx reset ack n status...
	INFO: TX fully in reset state 
	INFO: Channel 0: Set RX Reset
	INFO: Channel 0 : Checking rx reset ack n status...
	INFO: RX fully in reset state 
	Info: Channel: 0 Configuring ED to CPRI 24G_RSFEC ....
	Info: Wait for DR Ready....
	Info: Trigger DR interrupt
	Info: Wait for DR interrupt Ack....
		Info: DR Request acknowledged
	Info: Wait for DR Config to be done....
		Info: DONE Reconfigure to 24G_RSFEC.
	INFO: Channel 0: Configuring cpri_speed
	Info: Channel: 0 Loop: 0 De-asserting reset to CPRI 24G_RSFEC ....
	INFO: Channel 0: Release TX Reset
	Info: Check TX Ready Attempt: 1
	INFO: Channel 0 : Checking TX ready status...
		Info: tx_ready = 1
	INFO: Channel 0: Release RX Reset
	Info: Check RX Ready Attempt: 1
	INFO: Channel 0 : Checking RX ready status...
		Info: rx_ready = 1
	INFO: Channel 0 : Checking RX PCS ready status...
		Info: rx_pcs_ready  = 1
	Info:Info: Channel: 0 Configuring DL ....
	Info:Info: Channel: 0 Programing RSFEC WA into DL counter ....
	Info:Info: Channel: 0 Starting DL ....
	Info Channel: 0 sending packets in progress, waiting for checker pass ***
	Info Channel: 0 waiting for measure_valid to assert...
	INFO: Channel 0 : Checking hyperframe sync status...
	INFO: hyperframe sync asserted
	INFO: Channel 0 : Checking RT count done status...
	INFO: RT count done asserted
	Channel 0 : Read Determenistic latency counts
	Channel 0 : Get checker_pass status:
	Checker value = 0
	Checker status = Passed!

**
*****************************************

Info: End of ftile_cpri_dr_test
Info: Test <ftile_cpri_dr_test> Passed
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