F-Tile SDI II Intel® Agilex™ FPGA IP Design Example User Guide

ID 710496
Date 1/28/2022
Public

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2.3. Functional Description

The SDI II Intel® FPGA IP core design example supports the following simplex and duplex transceiver mode:.
  • Parallel loopback with simplex mode
  • Parallel loopback with duplex mode
  • Serial loopback with simplex mode
  • Serial loopback with duplex mode
Figure 12. Parallel Loopback with Simplex Mode
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
Figure 13. Parallel Loopback with Duplex Mode
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
Figure 14. Serial Loopback with Simplex Mode
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.
Figure 15. Serial Loopback with Duplex Mode
Note: Refer to Clocking Scheme for the Reference and System PLL Clocks IP connections.