F-Tile HDMI Intel® FPGA IP Design Example User Guide

Download PDF
ID 709314
Date 4/03/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) 3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) 4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL and TMDS
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full) x
3.1. Design Features 3.2. Hardware and Software Requirements 3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams 3.4. Design Parameters 3.5. Design Components 3.6. Design Software Flow 3.7. Clocking Scheme 3.8. Interface Signals 3.9. Hardware Setup
3.3. HDMI 2.1 RX-TX Retransmit Design Block Diagrams x
3.3.1. HDMI 2.1 RX-TX Direct Retransmit Design Block Diagram (Without Video Frame Buffer) 3.3.2. HDMI 2.1 RX-TX Retransmit Design Block Diagram (With Video Frame Buffer)
3.4. Design Parameters x
3.4.1. HDMI RX Direction 3.4.2. HDMI TX Direction
3.6. Design Software Flow x
3.6.1. Configure Redriver Setting 3.6.2. Initialize TX Path 3.6.3. Initialize RX Path 3.6.4. Initialize HDMI TX Register 3.6.5. Wait for RX Path Ready 3.6.6. TX Reconfiguration and Link Training 3.6.7. Set TX Video Clock 3.6.8. Set AXI2CV Configuration 3.6.9. HDMI TX Transmit Video
3.7. Clocking Scheme x
3.7.1. HDMI 2.1 RX-TX Retransmit Design without Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same Clock = ON) 3.7.2. HDMI 2.1 RX-TX Retransmit Design with Video Frame Buffer (Enable Active Video Protocol = AXIS-VVP Full, Video In and Out Use the Same = OFF) 3.7.3. Clock Details
3.8. Interface Signals x
3.8.1. Platform Design System
3.9. Hardware Setup x
3.9.1. Supporting Additional Video Resolutions
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel Agilex® 7 F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1, Enable Active Video Protocol = None)
3. HDMI 2.1 Design Example with AXI4-stream Interface Enabled (Support FRL =1, Enable Active Video Protocol = AXIS-VVP Full)
4. Document Revision History for the F-Tile HDMI Intel® FPGA IP Design Example User Guide

2.3.1. Creating RX-Only or TX-Only Designs

For advanced users, you can use the Intel Agilex® 7 HDMI RX-TX Retransmit design to create a TX or RX-only design.

To create an RX-only design, remove the HDMI TX Top and RX-TX Link modules. However, you need the CPU Subsystem to set the EDID value for the RX Core.

Figure 10. HDMI 2.1 RX-only Block Diagram
To create a TX-only design, remove the HDMI RX Top and RX-TX Link modules. However, you need the CPU Subsystem to read EDID from the Sink and for the Link Training Process.
Figure 11. HDMI 2.1 TX-only Block Diagram

To use RX or TX-only components, remove the irrelevant blocks from the design.

Table 8.  RX-Only and TX-Only Design Requirements
User Requirements Preserve Remove Add
HDMI RX only RX Top
  • TX Top
  • RX-TX Link
  • CPU Subsystem
  • Transceiver Arbiter
 —
HDMI TX only
  • TX Top
  • CPU Sub-System
  • RX Top
  • RX-TX Link
  • Transceiver Arbiter
 Video Pattern Generator

(custom module or generated from the Video and Image Processing (VIP) Suite)

Aside from the RTL changes, you need to also edit the main.c script.

  • For HDMI TX-only designs, decouple the wait for the HDMI RX lock status by doing the following:
    1. Remove the following lines:

      rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET, PIO_RX_LOCKED_WIDTH);

      while (rx_hdmi_lock == 0) {

      if (check_hpd_isr()) { break; }

      // rx_vid_lock = READ_PIO(PIO_IN0_BASE, PIO_VID_LOCKED_OFFSET, PIO_VID_LOCKED_WIDTH);

      rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET, PIO_RX_LOCKED_WIDTH);

      // Reconfig Tx after rx is locked

      if (rx_hdmi_lock == 1) {

      if (READ_PIO(PIO_IN0_BASE, PIO_LOOPBACK_MODE_OFFSET, PIO_LOOPBACK_MODE_WIDTH) == 1) {

      rx_frl_rate = READ_PIO(PIO_IN0_BASE, PIO_RX_FRL_RATE_OFFSET, PIO_RX_FRL_RATE_WIDTH);

      tx_xcvr_reconfig(rx_frl_rate);

      } else {

      tx_xcvr_reconfig(tx_frl_rate);

      } } }

    2. Replace with:

      tx_xcvr_reconfig(tx_frl_rate);

  • For HDMI RX-only designs, keep only the following lines in the main.c script:

    REDRIVER_INIT();

    hdmi_rx_init();

Level Two Title