HDMI Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

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ID 709314
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. Document Revision History for the HDMI Agilex F-tile Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.5.2.1. RX PHY Adapter x
2.5.2.1.1. FRL
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. Document Revision History for the HDMI Agilex F-tile Design Example User Guide

2.9. Hardware Setup

The HDMI FRL-enabled design example is HDMI 2.1 capable and performs a loop-through demonstration for a standard HDMI video stream.
To run the hardware test, connect an HDMI-enabled device—such as a graphics card with HDMI interface—to the HDMI sink input. The design supports both HDMI 2.1 or HDMI 2.0/1.4b source and sink.
  1. The HDMI sink decodes the port into a standard video stream and sends it to the clock recovery core.
  2. The HDMI RX core decodes the video, auxiliary, and audio data to be looped back in parallel to the HDMI TX core through the DCFIFO.
  3. The HDMI source port of the FMC daughter card transmits the image to a monitor.
Note: If you want to use another Intel FPGA development board, you must change the device assignments and the pin assignments. The transceiver analog setting is tested for the Intel® Agilex™ GX FPGA development kit and Bitec HDMI 2.1 daughter card. You may modify the settings for your own board.
On-board Push Button and User LED Functions
Push Button/LED Function
cpu_resetn Press once to perform system reset.
user_dipsw[0] User-defined DIP switch to toggle the passthrough mode.
  • OFF (default position) = Passthrough

    HDMI RX on the FPGA gets the EDID from external sink and presents it to the external source it is connected to.

  • ON = You may control the RX maximum FRL rate from the Nios® II terminal. The command modifies the RX EDID by manipulating the maximum FRL rate value.
user_dipsw[1] User-defined DIP switch to toggle the passthrough mode.
  • OFF (default position) = user_led[3:0] indicates RX status.
  • ON = user_led[3:0] indicates TX status.

Refer to user_led[3:0] for more details.
user_pb[0] Press once to toggle the HPD signal to the standard HDMI source.
user_pb[1] Reserved.
user_pb[2]
Press once to read the SCDC registers from the sink connected to the TX of the Bitec HDMI 2.1 FMC daughter card.
Note: To enable read, you must set DEBUG_MODE to 1 in the software.
user_led[0] user_dipsw[1] = ON
RX transceiver ready status.
  • 0 = Not ready
  • 1 = Ready
user_dipsw[1] = OFF
TX transceiver ready status.
  • 0 = Not ready
  • 1 = Ready
user_led[1] user_dipsw[1] = ON
RX FRL clock PLL lock status.
  • 0 = Unlocked
  • 1 = Locked
user_dipsw[1] = OFF
TX FRL clock PLL lock status.
  • 0 = Unlocked
  • 1 = Locked
user_led[2] user_dipsw[1] = ON
RX HDMI core alignment and deskew lock status.
  • 0 = At least 1 channel is unlocked
  • 1 = All channels are locked
user_dipsw[1] = OFF
TX FRL start status.
  • 0 = TX core transmits link training pattern
  • 1 = TX core transmits normal video
user_led[3] user_dipsw[1] = ON
RX HDMI video lock status.
  • 0 = Unlocked
  • 1 = Locked
user_dipsw[1] = OFF Reserved.
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