HDMI Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

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ID 709314
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. Document Revision History for the HDMI Agilex F-tile Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.5.2.1. RX PHY Adapter x
2.5.2.1.1. FRL
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. Document Revision History for the HDMI Agilex F-tile Design Example User Guide

2.11.3. Clock Frequency Measurement

Use this feature to check the frequency for the different clocks.
  1. In the hdmi_rx_top and hdmi_tx_top files, uncomment //`define DEBUG_EN 1.
  2. Add the refclock_measure signal from each mr_rate_detect instance to the Signal Tap Logic Analyzer to get the clock frequency of each clock (in 10 ms duration).
  3. Compile the design with Signal Tap Logic Analyzer.
  4. Program the SOF file and run the Signal Tap Logic Analyzer.
Table 21.  Clocks
Module mr_rate_detect Instance Clock to be Measured
hdmi_rx_top rx_pll_tmds RX CDR reference clock 0
rx_clk0_freq RX transceiver clock out from channel 0
rx_vid_clk_freq RX video clock
rx_frl_clk_freq RX FRL clock
rx_hsync_freq Hsync frequency of the received video frame
hdmi_tx_top tx_clk0_freq TX transceiver clock out from channel 0
vid_clk_freq TX video clock
frl_clk_freq TX FRL clock
tx_hsync_freq Hsync frequency of the video frame to be transmitted
Level Two Title