HDMI Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

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ID 709314
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices 2. HDMI 2.1 Design Example (Support FRL = 1) 3. Document Revision History for the HDMI Agilex F-tile Design Example User Guide
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices x
1.1. Directory Structure 1.2. Generating the Design 1.3. Simulating the Design 1.4. Compiling and Testing the Design
2. HDMI 2.1 Design Example (Support FRL = 1) x
2.1. Design Features 2.2. Hardware and Software Requirements 2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram 2.4. Design Parameters 2.5. Design Components 2.6. Design Software Flow 2.7. Clocking Scheme 2.8. Interface Signals 2.9. Hardware Setup 2.10. Simulation Testbench 2.11. Debugging Features
2.3. HDMI 2.1 RX-TX Retransmit Design Block Diagram x
2.3.1. Creating RX-Only or TX-Only Designs
2.4. Design Parameters x
2.4.1. IP Parameters 2.4.2. HDMI Intel® FPGA IP Design Example Parameters
2.5. Design Components x
2.5.1. HDMI TX Components 2.5.2. HDMI RX Components 2.5.3. Top-Level Common Blocks
2.5.1. HDMI TX Components x
2.5.1.1. TX PHY Adapter
2.5.1.1. TX PHY Adapter x
2.5.1.1.1. FRL
2.5.2. HDMI RX Components x
2.5.2.1. RX PHY Adapter
2.5.2.1. RX PHY Adapter x
2.5.2.1.1. FRL
2.11. Debugging Features x
2.11.1. Software Debug Message 2.11.2. SCDC Information from Sink Connected to TX 2.11.3. Clock Frequency Measurement
1. HDMI Intel® FPGA IP Design Example Quick Start Guide for Intel® Agilex™ F-tile Devices
2. HDMI 2.1 Design Example (Support FRL = 1)
3. Document Revision History for the HDMI Agilex F-tile Design Example User Guide

2.3.1. Creating RX-Only or TX-Only Designs

For advanced users, you can use the HDMI 2.1 design to create a TX- or RX-only design.

For RX-only design, you can remove the HDMI TX Top and RX-TX Link module. However, you need the CPU Subsystem to set the EDID value for the RX Core.

Figure 6. HDMI 2.1 RX-only Block Diagram
For TX-only design, you can remove the HDMI RX Top and RX-TX Link module. However, you need the CPU Subsystem to read EDID from the Sink and for the Link Training Process.
Figure 7. HDMI 2.1 TX-only Block Diagram

To use RX- or TX-only components, remove the irrelevant blocks from the design.

Table 6.  RX-Only and TX-Only Design Requirements
User Requirements Preserve Remove Add
HDMI RX only RX Top
  • TX Top
  • RX-TX Link
  • CPU Subsystem
  • Transceiver Arbiter
 –
HDMI TX only
  • TX Top
  • CPU Sub-System
  • RX Top
  • RX-TX Link
  • Transceiver Arbiter
 Video Pattern Generator

(custom module or generated from the Video and Image Processing (VIP) Suite)

Besides the RTL changes, you need to also edit the main.c script.

  • For HDMI TX-only designs, decouple the wait for the HDMI RX lock status by removing the following lines and replace with tx_xcvr_reconfig(tx_frl_rate);

    rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET, PIO_RX_LOCKED_WIDTH);

    while (rx_hdmi_lock == 0) {

    if (check_hpd_isr()) { break; }

    // rx_vid_lock = READ_PIO(PIO_IN0_BASE, PIO_VID_LOCKED_OFFSET, PIO_VID_LOCKED_WIDTH);

    rx_hdmi_lock = READ_PIO(PIO_IN0_BASE, PIO_RX_LOCKED_OFFSET, PIO_RX_LOCKED_WIDTH);

    // Reconfig Tx after rx is locked

    if (rx_hdmi_lock == 1) {

    if (READ_PIO(PIO_IN0_BASE, PIO_LOOPBACK_MODE_OFFSET, PIO_LOOPBACK_MODE_WIDTH) == 1) {

    rx_frl_rate = READ_PIO(PIO_IN0_BASE, PIO_RX_FRL_RATE_OFFSET, PIO_RX_FRL_RATE_WIDTH);

    tx_xcvr_reconfig(rx_frl_rate);

    } else {

    tx_xcvr_reconfig(tx_frl_rate);

    } } }

  • For HDMI RX-only designs, keep only the following lines in the main.c script:

    REDRIVER_INIT();

    hdmi_rx_init();

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