DisplayPort Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

Download PDF
ID 709308
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. Document Revision History for the DisplayPort Intel® Agilex™ F-tile FPGA IP Design Example User Guide
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Simulating the Design 1.6. DisplayPort Intel FPGA IP Design Example Parameters
2. Parallel Loopback Design Examples x
2.1. Intel® Agilex™ F-tile DisplayPort SST Parallel Loopback Design Features 2.2. Clocking Scheme 2.3. Simulation Testbench
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. Document Revision History for the DisplayPort Intel® Agilex™ F-tile FPGA IP Design Example User Guide

1.4. Simulating the Design

The DisplayPort Intel® FPGA IP design example testbench simulates a serial loopback design from a TX instance to an RX instance. An internal video pattern generator module drives the DisplayPort TX instance and the RX instance video output connects to CRC checkers in the testbench.
Figure 4. Design Simulation Flow
  1. Go to Synopsys simulator folder and select VCS.
  2. Run simulation script.
    Source vcs_sim.sh
  3. The script performs Quartus TLG, compiles and run the testbench in the simulator.
  4. Analyze the result.
A successful simulation ends with Source and Sink SRC comparison.
Level Two Title