DisplayPort Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

ID 709308
Date 12/13/2021
Public

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1.1. Directory Structure

Figure 2. Directory Structure
Table 1.  Design Example Components
Folders Files
rtl/core dp_core.ip
dp_rx.ip
dp_tx.ip
rtl/rx_phy dp_gxb_rx/ ((DP PMA UX building block)
dp_rx_data_fifo.ip
rx_top_phy.sv
rtl/tx_phy dp_gxb_rx/ ((DP PMA UX building block)
dp_tx_data_fifo.ip
dp_tx_data_fifo.ip