DisplayPort Intel® Agilex™ F-Tile FPGA IP Design Example User Guide

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ID 709308
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. Document Revision History for the DisplayPort Intel® Agilex™ F-tile FPGA IP Design Example User Guide
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Simulating the Design 1.6. DisplayPort Intel FPGA IP Design Example Parameters
2. Parallel Loopback Design Examples x
2.1. Intel® Agilex™ F-tile DisplayPort SST Parallel Loopback Design Features 2.2. Clocking Scheme 2.3. Simulation Testbench
1. DisplayPort Intel FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. Document Revision History for the DisplayPort Intel® Agilex™ F-tile FPGA IP Design Example User Guide

2.1. Intel® Agilex™ F-tile DisplayPort SST Parallel Loopback Design Features

The SST parallel loopback design examples demonstrate the transmission of a single video stream from DisplayPort sink to DisplayPort source without Pixel Clock Recovery (PCR) at static rate.
Figure 6.  Intel® Agilex™ F-tile DisplayPort SST Parallel Loopback without PCR
  • In this variant, the DisplayPort source’s parameter, TX_SUPPORT_IM_ENABLE, is turned on and the video image interface is used.
  • The DisplayPort sink receives video and or audio streaming from external video source such as GPU and decodes it into parallel video interface.
  • The DisplayPort sink video output directly drives the DisplayPort source video interface and encodes to the DisplayPort main link before transmitting to the monitor.
  • The IOPLL drives both the DisplayPort sink and source video clocks at a fixed frequency.
  • If DisplayPort sink and source's MAX_LINK_RATE parameter is configured to HBR3 and PIXELS_PER_CLOCK is configured to Quad, the video clock runs at 300 MHz to support 8Kp30 pixel rate (1188/4 = 297 MHz).
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