DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683887
Date 5/11/2021
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices 4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Creating RX-Only or TX-Only Designs 2.3. Design Components 2.4. Clocking Scheme 2.5. Interface Signals and Parameters 2.6. Hardware Setup 2.7. Simulation Testbench 2.8. DisplayPort Transceiver Reconfiguration Flow 2.9. Transceiver Lane Configurations
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features x
2.1.1. Enabling Adaptive Sync Support
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Security Considerations 3.7. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.5. View the Results x
3.4.5.1. LED Functions
3.7. Debug Guidelines x
3.7.1. HDCP Status Signals 3.7.2. Modifying HDCP Software Parameters 3.7.3. HDCP Key Mapping from DCP Key Files 3.7.4. Frequently Asked Questions (FAQ)
3.7.3. HDCP Key Mapping from DCP Key Files x
3.7.3.1. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.7.3.2. hdcp2x_rx_kmem.v file 3.7.3.3. hdcp2x_tx_kmem.v file
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)

Figure 16. High Level Overview of HDCP Key Management

When Support HDCP Key Management parameter is turned on, you hold control of HDCP production key encryption by using the key encryption (KEYENC) design that Intel provides. You must provide the HDCP production keys and a 128 bits HDCP protection key. The HDCP protection key encrypts the HDCP production key and the encrypted key is stored in the external flash memory (ie. EEPROM) on DisplayPort daughter card.

Turn on the Support HDCP Key Management parameter and the key decryption feature (KEYDEC) becomes available in the HDCP IP cores. You must use the same HDCP protection key in the KEYDEC to retrieve the HDCP production keys at run time for processing engines. KEYENC and KEYDEC support Atmel AT24CS32 32-Kbit serial EEPROM, Atmel AT24C16A 16-Kbit serial EEPROM and compatible I2C EEPROM devices with at least 16-Kbit rom size.

To include the HDCP production keys in the KEYENC design and program the encrypted HDCP production keys onto the EEPROM, follow these steps:

  1. Copy the hardware demonstration files from the following path to your working directory: <IP Root Directory>/hdcp2x/hw_demo/key_encryption/<Device Family Name>
  2. Locate the top level design file (<Device Family Name>_hdcp_key_encryption.v) in the rtl/ directory and modify the parameter DAUGHTER_CARD_TYPE to 1.
  3. Locate the software file (main.c) in the software/key_encrypt_src/ directory and modify the software parameter #EEPROM_REVISION to 1.
  4. Locate the software header file (hdcp_keys.h) in the software/key_encrypt_src/ directory and include your HDCP production keys and HDCP protection key in big endian format as shown in the examples below.
    Figure 17. Data array of Facsimile Key R1 for RX Private Key
    Figure 18. Data arrays of HDCP Production Keys (Placeholder)
    Figure 19. Data array of HDCP Protection Key (Predefined key)
  5. Run ./runall.tcl. This script executes the following commands:
    • Generate IP catalog files
    • Generate the Platform Designer system
    • Create an Intel® Quartus® Prime project
    • Create a software workspace and build the software
    • Perform a full compilation
  6. Download the Software Object File (.sof) to the FPGA to program the encrypted HDCP production keys onto the EEPROM.
  7. To generate the EEPROM image file, edit the read_mem.tcl to make sure the hardware_name and device_name are matching to the running hardware.
  8. Run "quartus_stp -t read_mem.tcl". The script generates an EEPROM image file in .hex file format under the same directory.

Generate the DisplayPort SST Parallel Loopback With PCR design example with Support HDCP 2.3 and Support HDCP 1.4 parameters turned on, then follow these steps to include the HDCP protection key.

  1. Locate the following Memory Initialization Files (.mif) in the <project directory>/rtl/hdcp/ directory:
    • hdcp2x_rx_kmem.mif
    • hdcp2x_tx_kmem.mif
    • hdcp1x_rx_kmem.mif
    • hdcp1x_tx_kmem.mif
  2. Open the hdcp2x_rx_kmem.mif file. Locate the predefined HDCP protection key as shown in the example below and replace with your HDCP protection key in big endian format.
    Figure 20. HDCP protection key initialized in hdcp2x_rx_kmem.mif
  3. Repeat Step 2 for the other memory initialization files as shown in the examples below.
    Figure 21. HDCP protection key initialized in hdcp2x_tx_kmem.mif
    Figure 22. HDCP protection key initialized in hdcp1x_rx_kmem.mif
    Figure 23. HDCP protection key initialized in hdcp1x_tx_kmem.mif
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