DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683887
Date 5/11/2021
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices 4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features 2.2. Creating RX-Only or TX-Only Designs 2.3. Design Components 2.4. Clocking Scheme 2.5. Interface Signals and Parameters 2.6. Hardware Setup 2.7. Simulation Testbench 2.8. DisplayPort Transceiver Reconfiguration Flow 2.9. Transceiver Lane Configurations
2.1. Intel® Stratix® 10 DisplayPort SST Parallel Loopback Design Features x
2.1.1. Enabling Adaptive Sync Support
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios II Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Security Considerations 3.7. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Set Up the Hardware 3.4.2. Generate the Design 3.4.3. Include HDCP Production Keys 3.4.4. Compile the Design 3.4.5. View the Results
3.4.3. Include HDCP Production Keys x
3.4.3.1. Store plain HDCP production keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Store encrypted HDCP production keys in the external flash memory or EEPROM (Support HDCP Key Management = 1)
3.4.5. View the Results x
3.4.5.1. LED Functions
3.7. Debug Guidelines x
3.7.1. HDCP Status Signals 3.7.2. Modifying HDCP Software Parameters 3.7.3. HDCP Key Mapping from DCP Key Files 3.7.4. Frequently Asked Questions (FAQ)
3.7.3. HDCP Key Mapping from DCP Key Files x
3.7.3.1. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.7.3.2. hdcp2x_rx_kmem.v file 3.7.3.3. hdcp2x_tx_kmem.v file
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. HDCP Over DisplayPort Design Example for Intel® Stratix® 10 Devices
4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Revision History for the DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide

4. DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide Archives

IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to 19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.

If an IP core version is not listed, the user guide for the previous IP core version applies.
Intel® Quartus® Prime Version IP Core Version User Guide
20.3 19.4.0 DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
20.2 19.3.0 DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
20.1 19.3.0 DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
19.2 19.1.0 DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
19.1 19.1 DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
18.1 18.1 DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide
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