Visible to Intel only — GUID: ckk1671551240778
Ixiasoft
Answers to Top FAQs
1. FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Quartus® Prime Pro Edition User Guides
1.1. FPGA Simulation Essential Elements
1.2. Overview of Simulation Tool Flow
1.3. Simulation Tool Flow
1.4. Supported Simulation Flows
1.5. Supported Hardware Description Languages
1.6. Supported Simulation Types
1.7. Supported Simulators
1.8. Post-Fit Simulation Support by FPGA Family
1.9. Automating Simulation with the Run Simulation Feature
1.10. FPGA Simulation Basics Revision History
1.9.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode)
1.9.2.2. Optional Simulation Settings for Run Simulation (Batch Mode)
1.9.2.3. Launching Simulation with the Run Simulation Feature
1.9.2.4. Running RTL Simulation using Run Simulation
1.9.2.5. Output Directories and Files for Run Simulation
Visible to Intel only — GUID: ckk1671551240778
Ixiasoft
1.3.3.3. Running the Simulation Library Compiler in the GUI
To automatically compile all required simulation model libraries for your design in your supported simulator using the Simulation Library Compiler GUI, follow these steps:
- In the Quartus® Prime software, click Tools > Launch Simulation Library Compiler.
- Specify options for your simulation tool, language, target device family, and output location, and then click OK. Simulation model compilation may require up to an hour, depending on your system. Although the compilation messages may appear paused or incomplete, compilation is still running correctly.
- Use the compiled simulation model libraries to simulate your design. For information about running simulation, refer to your supported EDA simulator's documentation.
Figure 5. Simulation Library Compiler GUI