Quartus® Prime Pro Edition User Guide: Third-party Simulation

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ID 683870
Date 1/23/2025
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs 1. FPGA Simulation Basics 2. Siemens EDA QuestaSim* Simulator Support 3. Synopsys VCS* and VCS MX Support 4. Aldec Active-HDL and Riviera-PRO Support 5. Cadence Xcelium* Parallel Simulator Support 6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive A. Quartus® Prime Pro Edition User Guides
1. FPGA Simulation Basics x
1.1. FPGA Simulation Essential Elements 1.2. Overview of Simulation Tool Flow 1.3. Simulation Tool Flow 1.4. Supported Simulation Flows 1.5. Supported Hardware Description Languages 1.6. Supported Simulation Types 1.7. Supported Simulators 1.8. Post-Fit Simulation Support by FPGA Family 1.9. Automating Simulation with the Run Simulation Feature 1.10. Using Precompiled Simulation Libraries 1.11. FPGA Simulation Basics Revision History
1.2. Overview of Simulation Tool Flow x
1.2.1. Compilation Stage 1.2.2. Elaboration Stage 1.2.3. Simulation Stage
1.3. Simulation Tool Flow x
1.3.1. Specifying Logical Libraries 1.3.2. Compiling Files Into Library Directories 1.3.3. The Quartus® Prime Simulation Library 1.3.4. Understanding Elaboration 1.3.5. Commands To Configure and Run Simulation 1.3.6. FPGA Simulation Generic Workflow
1.3.1. Specifying Logical Libraries x
1.3.1.1. Why Do We Need Logical Library Names?
1.3.2. Compiling Files Into Library Directories x
1.3.2.1. Inputs to Compilation Commands 1.3.2.2. Order of Files for Compilation Commands 1.3.2.3. Compilation Command Line Options 1.3.2.4. Module Definitions in Library Directories
1.3.3. The Quartus® Prime Simulation Library x
1.3.3.1. The Quartus® Prime Simulation Library Compiler 1.3.3.2. Running the Simulation Library Compiler in a Terminal 1.3.3.3. Running the Simulation Library Compiler in the GUI 1.3.3.4. Finding Logical Library Names in Simulation Library Compiler Output
1.3.4. Understanding Elaboration x
1.3.4.1. Elaboration Binding Phase 1.3.4.2. Elaboration Checks 1.3.4.3. Elaboration Options
1.9. Automating Simulation with the Run Simulation Feature x
1.9.1. Setting Up the Run Simulation Feature 1.9.2. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line) 1.9.3. Simulating Intel FPGA IP Example Designs using the Run Simulation Feature
1.9.1. Setting Up the Run Simulation Feature x
1.9.1.1. Installation Paths for Supported EDA Simulators (EDA Tool Options Page) 1.9.1.2. Simulation Options (Board and IP Settings Page) 1.9.1.3. Simulation Flow Settings (EDA Tool Settings Page) 1.9.1.4. More EDA Netlist Writer Settings (EDA Tool Settings Page)
1.9.2. Run RTL Simulation using Run Simulation in Batch Mode (Command-Line) x
1.9.2.1. Specifying Required Simulation Settings for Run Simulation (Batch Mode) 1.9.2.2. Optional Simulation Settings for Run Simulation (Batch Mode) 1.9.2.3. Launching Simulation with the Run Simulation Feature 1.9.2.4. Running RTL Simulation using Run Simulation 1.9.2.5. Output Directories and Files for Run Simulation
1.10. Using Precompiled Simulation Libraries x
1.10.1. Enabling Precompiled Simulation Libraries 1.10.2. Implementing Precompiled Simulation Libraries Implementing Precompiled Simulation Libraries in the GUI Implementing Precompiled Simulation Libraries by Modifying Simulator Setup Script
2. Siemens EDA QuestaSim* Simulator Support x
2.1. Quick Start Example (QuestaSim* with Verilog) 2.2. QuestaSim* Simulator Guidelines 2.3. Using the Qrun Flow 2.4. QuestaSim* Simulation Setup Script Example 2.5. Sourcing QuestaSim* Simulator Setup Scripts 2.6. Unsupported Features 2.7. Siemens EDA QuestaSim* Simulator Support Revision History
2.2. QuestaSim* Simulator Guidelines x
2.2.1. Passing Parameter Information from Verilog HDL to VHDL 2.2.2. Viewing Simulation Messages 2.2.3. Generating Signal Activity Data for Power Analysis 2.2.4. Viewing Simulation Waveforms
2.3. Using the Qrun Flow x
2.3.1. Specifying Simulation File Generation Settings 2.3.2. Generating the Simulation Model and Setup Scripts 2.3.3. Generating the Testbench System 2.3.4. Generating Example Design Simulation Files 2.3.5. Recommendations for Using Qrun
3. Synopsys VCS* and VCS MX Support x
3.1. Quick Start Example (VCS with Verilog) 3.2. VCS and VCS MX Guidelines 3.3. VCS Simulation Setup Script Example 3.4. Sourcing Synopsys VCS* MX Simulator Setup Scripts 3.5. Sourcing Synopsys VCS* Simulator Setup Scripts 3.6. Synopsys VCS* and VCS MX Support Revision History
4. Aldec Active-HDL and Riviera-PRO Support x
4.1. Quick Start Example (Active-HDL VHDL) 4.2. Aldec Active-HDL and Riviera-PRO Guidelines 4.3. Using Simulation Setup Scripts 4.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts 4.5. Aldec Active-HDL* and Riviera-PRO * Support Revision History
5. Cadence Xcelium* Parallel Simulator Support x
5.1. Using the Command-Line Interface 5.2. Generating Simulator Setup Script Templates 5.3. Sourcing Cadence Xcelium* Simulator Setup Scripts 5.4. Cadence Xcelium* Parallel Simulator Support Revision History
Answers to Top FAQs
1. FPGA Simulation Basics
2. Siemens EDA QuestaSim* Simulator Support
3. Synopsys VCS* and VCS MX Support
4. Aldec Active-HDL and Riviera-PRO Support
5. Cadence Xcelium* Parallel Simulator Support
6. Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Quartus® Prime Pro Edition User Guides

1.10.2. Implementing Precompiled Simulation Libraries

You can implement use of the precompiled simulation libraries by mapping the precompiled library files in the Simulation Flow Settings GUI, or by modifying the simulator setup script files directly.

Implementing Precompiled Simulation Libraries in the GUI

  1. In the Quartus® Prime Pro Edition software, click Assignments > Settings > EDA Tool Settings > Simulation > Simulation Flow Settings.
  2. Click the User precompiled simulation library mapping file option for your simulator and specify the precompiled simulation mapping file path in the Setting column.
    Figure 12. User Precompiled Simulation Library Mapping File Setting


    Table 13.  Precompiled Library Files to Add by Simulator
    Simulator Precompiled Library File to Add
    Xcelium cds.lib
    Riviera-PRO library.cfg
    QuestaSim modelsim.ini
    VCS MX synopsys_sim.setup
  3. Click the Start Compilation button to perform one-time compilation of the device libraries. Subsequent compiles do not recompile these libraries.
  4. To run the simulation, refer to Run RTL Simulation using Run Simulation in Batch Mode.

Implementing Precompiled Simulation Libraries by Modifying Simulator Setup Script

The simulation setup scripts that the Quartus® Prime Pro Edition software now generates include the PRECOMP_DEVICE_LIB_FILE variable. This variable can hold different values, depending on your target simulator. You can specify the path for the precompiled simulation library file to reuse the precompiled library, rather than recompiling the device library each time.

  1. In a text editor, open the generated simulator setup script for your target simulator.
  2. In the simulator setup script, locate the PRECOMP_DEVICE_LIB_FILE variable.
  3. Specify the appropriate PRECOMP_DEVICE_LIB_FILE value for your target simulator:
    Table 14.  Simulator Setup Script and Precompile Simulation Option
    Simulator Setup Script Simulation Option
    Xcelium xcelium_setup.sh PRECOMP_DEVICE_LIB_FILE="<path ./cds.lib>"
    Riviera-PRO rivierapro_setup.tcl if ![info exists PRECOMP_DEVICE_LIB_FILE] { set PRECOMP_DEVICE_LIB_FILE "<path ./library.cfg>" }
    QuestaSim msim_setup.tcl if ![info exists PRECOMP_DEVICE_LIB_FILE] { set PRECOMP_DEVICE_LIB_FILE "<path ./modelsim.ini>" }
    VCS MX vcsmx_setup.sh PRECOMP_DEVICE_LIB_FILE="<path ./synopsys_sim.setup>"
  4. Save the updated simulator setup script file. Subsequent compiles do not recompile these libraries.
  5. Run the simulation setup script.
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