Quartus® Prime Pro Edition User Guide: Third-party Simulation

ID 683870
Date 7/08/2024
Public
Document Table of Contents

1.9.1.2. Simulation Options (Board and IP Settings Page)

The following options impact automated IP simulation model generation. Click Tools > Options > Board and IP Settings > IP Simulation to specify the whether to always generate IP simulation models when generating IP for one or more simulator..
Table 9.  Simulation Options (Board and IP Settings Page) Options Dialog Box
Option Allowed Values Description
Tool name

<None>5

Active-HDL* 6

Riviera-PRO*

QuestaSim*

Questa* Intel® FPGA Edition

VCS*/VCS* MX(4)

Custom(6)

Xcelium* (4)

Specifies the supported simulator to automatically run.
Format for output netlist

Verilog HDL

VHDL

Specifies Verilog or VHDL as the format for the output netlist. The setting does not apply to RTL simulation.
Output directory Any valid path Specifies the directory to store all output files for simulation. Default is simulation/<simulator>.
Map illegal HDL characters

Disabled (Default)

Enabled

When enabled, directs the EDA Netlist Writer to map illegal characters for VHDL or Verilog HDL. The setting does not apply to RTL simulation.

If you select VHDL for Format for output netlist, the EDA Netlist writer maps non-alphanumeric characters, including brackets ([]), parentheses, (()), angle brackets (<>), and braces ({}) to (_a) in VHDL Output Files. This option generates VHDL 1987 compatible names.

If you select Verilog HDL for Format for output netlist, the EDA Netlist writer maps the vertical bar (|), tilde (~), and colon (:) characters in hierarchical node names to the legal Verilog HDL characters z, x, and underscore (_) in Verilog Output Files. This option also maps other illegal non-alphanumeric characters, including brackets ([]), parentheses, (()), angle brackets (<>), and braces ({}) to underscore (_).

5 Not supported by Run Simulation
6 Only supported for Windows OS.