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1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Questa*-Intel® FPGA Edition, ModelSim* , and Questa* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides
3.1. Quick Start Example (ModelSim with Verilog)
3.2. Questa*-Intel® FPGA Edition, ModelSim, and Questa Simulator Guidelines
3.3. ModelSim Simulation Setup Script Example
3.4. Sourcing ModelSim* Simulator Setup Scripts
3.5. Unsupported Features
3.6. Questa*-Intel® FPGA Edition, ModelSim* , and Questa* Simulator Support Revision History
3.2.1. Using Questa*-Intel® FPGA Edition Precompiled Libraries
3.2.2. Passing Parameter Information from Verilog HDL to VHDL
3.2.3. Viewing Simulation Messages
3.2.4. Generating Signal Activity Data for Power Analysis
3.2.5. Viewing Simulation Waveforms
3.2.6. Simulating with Questa*-Intel® FPGA Edition Waveform Editor
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4.5. Sourcing Synopsys VCS* Simulator Setup Scripts
Follow these steps to incorporate the generated Synopsys VCS* simulation scripts into a top-level project simulation script.
- The generated simulation script contains these template lines. Cut and paste the lines preceding the “helper file” into a new executable file. For example, synopsys_vcs.f.
# # Start of template # # If the copied and modified template file is "vcs_sim.sh", run it # # as: ./vcs_sim.sh # # # # Override the top-level name # # specify a command file containing elaboration options # # (system verilog extension, and compile the top-level). # # Override the sim options, so the simulation # # runs forever (until $finish()). # source vcs_setup.sh # TOP_LEVEL_NAME=top # USER_DEFINED_ELAB_OPTIONS="'-f ../../../synopsys_vcs.f'" # USER_DEFINED_SIM_OPTIONS="" # # # helper file: synopsys_vcs.f # +systemverilogext+.sv # ../../../top.sv # # End of template
- Delete the first two characters of each line (comment and space) for the vcs.sh file, as shown below:
# Start of template # If the copied and modified template file is "vcs_sim.sh", run it # as: ./vcs_sim.sh # # Override the top-level name # specify a command file containing elaboration options # (system verilog extension, and compile the top-level). # Override the sim options, so the simulation # runs forever (until $finish()). source vcs_setup.sh TOP_LEVEL_NAME=top USER_DEFINED_ELAB_OPTIONS="'-f ../../../synopsys_vcs.f'" USER_DEFINED_SIM_OPTIONS=""
- Delete the first two characters of each line (comment and space) for the synopsys_vcs.f file, as shown below:
# helper file: synopsys_vcs.f +systemverilogext+.sv ../../../top.sv # End of template
- Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on the simulation’s top-level file. For example:
TOP_LEVEL_NAME=sim_top
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes required to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
- Run the resulting top-level script from the generated simulation directory by specifying the path to vcs_sim.sh.