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1. Answers to Top FAQs
2. Intel FPGA Simulation Basics
3. Questa*-Intel® FPGA Edition, ModelSim* , and Questa* Simulator Support
4. Synopsys VCS* and VCS MX Support
5. Aldec Active-HDL and Riviera-PRO Support
6. Cadence Xcelium* Parallel Simulator Support
7. Intel® Quartus® Prime Pro Edition User Guide Third-party Simulation Archive
A. Intel® Quartus® Prime Pro Edition User Guides
3.1. Quick Start Example (ModelSim with Verilog)
3.2. Questa*-Intel® FPGA Edition, ModelSim, and Questa Simulator Guidelines
3.3. ModelSim Simulation Setup Script Example
3.4. Sourcing ModelSim* Simulator Setup Scripts
3.5. Unsupported Features
3.6. Questa*-Intel® FPGA Edition, ModelSim* , and Questa* Simulator Support Revision History
3.2.1. Using Questa*-Intel® FPGA Edition Precompiled Libraries
3.2.2. Passing Parameter Information from Verilog HDL to VHDL
3.2.3. Viewing Simulation Messages
3.2.4. Generating Signal Activity Data for Power Analysis
3.2.5. Viewing Simulation Waveforms
3.2.6. Simulating with Questa*-Intel® FPGA Edition Waveform Editor
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5.4. Sourcing Aldec ActiveHDL* or Riviera Pro* Simulator Setup Scripts
Follow these steps to incorporate the generated ActiveHDL* or Riviera Pro* simulation scripts into a top-level project simulation script.
- The generated simulation script contains the following template lines. Cut and paste these lines into a new file. For example, sim_top.do.
# # Start of template # # If the copied and modified template file is "aldec.do", run it as: # # vsim -c -do aldec.do # # # # Source the generated sim script # source rivierapro_setup.tcl # # Compile eda/sim_lib contents first # dev_com # # Override the top-level name (so that elab is useful) # set TOP_LEVEL_NAME top # # Compile the standalone IP. # com # # Compile the top-level # vlog -sv2k5 ../../top.sv # # Elaborate the design. # elab # # Run the simulation # run # # Report success to the shell # exit -code 0 # # End of template
- Delete the first two characters of each line (comment and space):
# Start of template # If the copied and modified template file is "aldec.do", run it as: # vsim -c -do aldec.do # # Source the generated sim script source rivierapro_setup.tcl # Compile eda/sim_lib contents first dev_com # Override the top-level name (so that elab is useful) set TOP_LEVEL_NAME top # Compile the standalone IP. com # Compile the top-level vlog -sv2k5 ../../top.sv # Elaborate the design. elab # Run the simulation run # Report success to the shell exit -code 0 # End of template
- Modify the TOP_LEVEL_NAME and compilation step appropriately, depending on the simulation’s top-level file. For example:
set TOP_LEVEL_NAME sim_top vlog –sv2k5 ../../sim_top.sv
- If necessary, add the QSYS_SIMDIR variable to point to the location of the generated IP simulation files. Specify any other changes that you require to match your design simulation requirements. The scripts offer variables to set compilation or simulation options. Refer to the generated script for details.
- Run the new top-level script from the generated simulation directory:
vsim –c –do <path to sim_top>.tcl