E-Tile Hard IP Intel Agilex® 7 Design Example User Guide: Ethernet, E-tile CPRI PHY and Dynamic Reconfiguration

ID 683860
Date 5/26/2023
Public

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4.5. 100G Ethernet Dynamic Reconfiguration Design Example

The 100G Ethernet E-Tile Dynamic Reconfiguration Design Example demonstrates a dynamic reconfiguration solution for Intel Agilex® 7 devices using the E-tile Ethernet IP for Intel Agilex® 7 FPGA core with the following variants. The 100G Ethernet E-Tile Dynamic Reconfiguration Design Example supports four PMA channels to create either a single 100G Ethernet channel, or four single 10G/25G Ethernet channels.

Table 43.  List of Supported Design Example Variants for 100G Ethernet Dynamic ReconfigurationAll variants support 156.25 MHz refclk and optional RS-FEC. The external AIB clocking, PTP, and asynchronous clock support are not available in the current implementation.
Base Operation Dynamic Reconfiguration Variants
100G MAC+PCS+(528,514)RS-FEC [NRZ] 100G MAC+PCS+(528,514)RS-FEC [NRZ]
100G MAC+PCS+(544,514)RS-FEC [PAM4]
100G MAC+PCS+(544,514)RS-FEC [NRZ]
100G MAC+PCS [NRZ]
4x25G MAC + PCS with RS-FEC [NRZ]
4x25G MAC + PCS [NRZ]

When a CSR reset occurs during or after a dynamic reconfiguration transition(DR), you must first perform a DR transition to the base operation mode (100G MAC+PCS+(528,514)RS-FEC [NRZ]) before proceeding to the other supported configurations. Failure to complete this step may result in errors during the DR transition to other supported configurations.

Figure 43. E-Tile 100G Dynamic Reconfiguration Transition Summary
Note: No direct Dynamic Reconfiguration transitions supported between the following speed/mode:
  • 100G MAC+PCS+(544,514)RS-FEC [PAM4] ←→ 4x25G MAC+PCS with RS-FEC [NRZ]
  • 100G MAC+PCS+(544,514)RS-FEC [PAM4] ←→ 4x25G MAC+PCS [NRZ]
  • 100G MAC+PCS+(544,514)RS-FEC [NRZ] ←→ 4x25G MAC+PCS with RS-FEC [NRZ]
  • 100G MAC+PCS+(544,514)RS-FEC [NRZ] ←→ 4x25G MAC+PCS [NRZ]
  • 100G MAC+PCS+(544,514)RS-FEC [PAM4] ←→ 100G MAC+PCS+(544,514)RS-FEC [NRZ]