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2.1.1. Directory Structure
2.1.2. Generating the Design
2.1.3. Simulating the E-tile Ethernet IP for Intel Agilex FPGA Design Example Testbench
2.1.4. Compiling the Compilation-Only Project
2.1.5. Compiling and Configuring the Design Example in Hardware
2.1.6. Testing the E-tile Ethernet IP for Intel Agilex FPGA Hardware Design Example
2.2.1.1. Non-PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.2. PTP 10GE/25GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.2.1.3. 10GE/25GE PCS Only, OTN, or FlexE with Optional RS-FEC Simulation Design Example
2.2.1.4. 10GE/25GE Custom PCS with Optional RS-FEC Simulation Design Example
2.3.1. Simulation Design Examples
2.3.2. Hardware Design Examples
2.3.3. 100GE MAC+PCS with Optional RS-FEC Design Example Interface Signals
2.3.4. 100GE PCS with Optional RS-FEC Design Example Interface Signals
2.3.5. 100GE MAC+PCS with Optional RS-FEC Design Example Registers
2.3.6. 100GE PCS with Optional RS-FEC Design Example Registers
2.3.1.1. Non-PTP E-tile Ethernet IP for Intel Agilex FPGA 100GE MAC+PCS with Optional RS-FEC Simulation Design Example
2.3.1.2. E-tile Ethernet IP for Intel Agilex FPGA 100GE MAC+PCS with Optional RS-FEC and PTP Simulation Design Example
2.3.1.3. E-tile Ethernet IP for Intel Agilex FPGA 100GE PCS Only with Optional RS-FEC Simulation Design Example
2.3.1.4. E-tile Ethernet IP for Intel Agilex FPGA 100GE OTN with Optional RS-FEC Simulation Design Example
2.3.1.5. E-tile Ethernet IP for Intel Agilex FPGA 100GE FlexE with Optional RS-FEC Simulation Design Example
2.3.2.1. 100GE MAC+PCS with Optional RS-FEC and PMA Adaptation Flow Hardware Design Example Components
2.3.2.2. 100GE MAC+PCS with Optional RS-FEC and PTP Hardware Design Example
2.3.2.3. 100GE PCS with Optional RS-FEC Hardware Design Example Components
2.3.2.4. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example
3.1.1. Hardware and Software Requirements
3.1.2. Generating the Design
3.1.3. Directory Structure
3.1.4. Simulating the Design Example Testbench
3.1.5. Compiling the Compilation-Only Project
3.1.6. Compiling and Configuring the Design Example in Hardware
3.1.7. Testing the E-tile CPRI PHY Intel® FPGA IP Hardware Design Example
4.1. Quick Start Guide
4.2. 10G/25G Ethernet Dynamic Reconfiguration Design Examples
4.3. 25G Ethernet to CPRI Dynamic Reconfiguration Design Example
4.4. CPRI Dynamic Reconfiguration Design Examples
4.5. 100G Ethernet Dynamic Reconfiguration Design Example
4.6. Document Revision History for the E-tile Dynamic Reconfiguration Design Example
4.5.1. Functional Description
4.5.2. Testing the 100G Ethernet Dynamic Reconfiguration Hardware Design Example
4.5.3. Simulation Design Examples
4.5.4. 100GE DR Hardware Design Examples
4.5.5. 100G Ethernet Dynamic Reconfiguration Design Example Interface Signals
4.5.6. 100G Ethernet Dynamic Reconfiguration Examples Registers
4.5.7. Steps to Enable FEC
4.5.8. Steps to Disable FEC
RS-FEC configuration to disable RS-FEC:
Transceiver configuration:
Ethernet configuration:
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4.5.8. Steps to Disable FEC
The following steps provide a procedure for disabling FEC for the 100G variant as handled in the C-code generated in the IP folder (dynamic_reconfig.cpp). This procedure is executed based on the values configured through the dynamic reconfiguration registers as per the software routines in the Design Example.
RS-FEC configuration to disable RS-FEC:
- [R1] Bypass FEC - Write 0x0000 to RS-FEC register 0x14 ([rsfec_top_rx_cfg]
- [R2] Disable FEC clock - Write 0x0000 to RS-FEC register 0x04 ([rsfec_top_clk_cfg]
Transceiver configuration:
- [T1] Write 0xCB to Transceiver channel register 0x4[7:0]
- [T2] Write 0x4C to Transceiver channel register 0x5[7:0]
- [T3] Write 0x0F to Transceiver channel register 0x6[7:0]
- [T4] Write 0xA6 to Transceiver channel register 0x7[7:0]
- [T5] Write 0xA5 to Transceiver channel register 0xA4[7:0]
- [T6] Write 0xA5 to Transceiver channel register 0xA8[7:0]
- [T7] Write 0x55 to Transceiver channel register 0xB0[7:0]
- [T8] Write 0x07 to Transceiver channel register 0xE8[7:0]
Note: Repeat steps 2a to 2h for each Transceiver channel.
Ethernet configuration:
- [E1] Write 0x312C7 to Ethernet register 0x37A
- [E2] Write 0x9FFD8028 to Ethernet register 0x40B
- [E3] Set bits [3] and [9] of Ethernet register 0x30E (Use RX PCS Alignment)