FPGA Interface Manager Data Sheet: Intel FPGA Programmable Acceleration Card D5005

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ID 683858
Date 8/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FIM and AFU Parameter Data 3. FPGA Interface Manager (FIM) Resource Utilization 4. Document Revision History for FPGA Interface Manager Data Sheet: Intel FPGA Programmable Acceleration Card D5005
2. FIM and AFU Parameter Data x
2.1. Memory Interface 2.2. Core Cache Interface (CCI-P) Interface 2.3. Clocks 2.4. Reset 2.5. Networking Interface
2.1. Memory Interface x
2.1.1. SDRAM Signals
2.5. Networking Interface x
2.5.1. Clock Signals 2.5.2. Data Interface and Signals 2.5.3. Control and Status Signals
1. Overview
2. FIM and AFU Parameter Data
3. FPGA Interface Manager (FIM) Resource Utilization
4. Document Revision History for FPGA Interface Manager Data Sheet: Intel FPGA Programmable Acceleration Card D5005

2.1. Memory Interface

Table 1.  Local Memory Interface Specifications
Parameter Value
Memory Protocol DDR4-SDRAM
AFU Interface Type Avalon® Memory Mapped Interface ( Avalon® -MM)
Number of Memory Interfaces 4
Density per Memory Interface 8 GB
AFU-Accessible Memory Address Bus Width 27-bit
AFU-accessible memory Data Width 576 bits (512 data bits + 64 ECC bits)
DDR Data Width 72-bits (64-data bits + 8 ECC bits)
DDR Frequency 1200 MHz maximum
Frequency

(AFU memory clock frequency)

300 MHz
Maximum Burst Size 64 beats
Address Mapping CS-CID-Row-Bank-Col-BG
Level Two Title