FPGA Interface Manager Data Sheet: Intel FPGA Programmable Acceleration Card D5005

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ID 683858
Date 8/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. FIM and AFU Parameter Data 3. FPGA Interface Manager (FIM) Resource Utilization 4. Document Revision History for FPGA Interface Manager Data Sheet: Intel FPGA Programmable Acceleration Card D5005
2. FIM and AFU Parameter Data x
2.1. Memory Interface 2.2. Core Cache Interface (CCI-P) Interface 2.3. Clocks 2.4. Reset 2.5. Networking Interface
2.1. Memory Interface x
2.1.1. SDRAM Signals
2.5. Networking Interface x
2.5.1. Clock Signals 2.5.2. Data Interface and Signals 2.5.3. Control and Status Signals
1. Overview
2. FIM and AFU Parameter Data
3. FPGA Interface Manager (FIM) Resource Utilization
4. Document Revision History for FPGA Interface Manager Data Sheet: Intel FPGA Programmable Acceleration Card D5005

2.2. Core Cache Interface (CCI-P) Interface

Table 3.   Core Cache Interface (CCI-P) Specifications
Parameter Value Notes
Width 512-bit CCI-P interface width.
Maximum CCI-P Frequency pClk -
Host Memory Cache-Line Size 64-byte -
Minimal write access size 1-byte

AFUs can write 1 byte to 63 bytes by setting the mode of TX channel 1 to a value of 1'b1

MMIO access width 32-bit and 64-bit 64-bit accesses are mandatory for Device Feature Header (DFH) enumeration.
MMIO Read Response Timeout 65536 clock cycles -
Virtual Channels Supported VH0, VA Accesses to VH0 and VA are mapped to the PCIe* link. Accesses to VH1 or VL0 are mapped to VH0.
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