AN 953: Partially Reconfiguring a Design: on an Intel Agilex® 7 FPGA Development Board

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ID 683849
Date 1/30/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board
Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board x
Reference Design Overview Reference Design Requirements Reference Design Files Reference Design Walkthrough Document Revision History for AN 953: Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Defining Personas Step 5: Creating Revisions Step 6: Compiling the Base Revision Step 7: Preparing PR Implementation Revisions Step 8: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 8: Programming the Board x
Troubleshooting PR Programming Errors
Answers to Top FAQs
Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board

Reference Design Overview

The reference design used in this tutorial consists of one 32-bit counter. At the board level, the design connects the clock to a 50 MHz source and the output to four LEDs on the board. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency.
Figure 1. Flat Reference Design without PR Partitioning

In this tutorial, the partial reconfiguration flow updates the function of u_blinking_led.

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