AN 953: Partially Reconfiguring a Design: on an Intel Agilex® 7 FPGA Development Board

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ID 683849
Date 1/30/2024
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Document Table of Contents
Document Table of Contents x
Answers to Top FAQs Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board
Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board x
Reference Design Overview Reference Design Requirements Reference Design Files Reference Design Walkthrough Document Revision History for AN 953: Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Defining Personas Step 5: Creating Revisions Step 6: Compiling the Base Revision Step 7: Preparing PR Implementation Revisions Step 8: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 8: Programming the Board x
Troubleshooting PR Programming Errors
Answers to Top FAQs
Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board

Reference Design Files

The reference design files required for this tutorial are available in the following location:

https://github.com/intel/fpga-partial-reconfig

To download the files:
  1. Click Code > Download ZIP.
  2. Unzip the fpga-partial-reconfig-master.zip file.
  3. Navigate to the appropriate sub-folder to access the reference designs for your target device:
    • tutorials/agilex7f_pcie_devkit_blinking_led
    • tutorials/agilex7m_pcie_devkit_blinking_led
Table 1.  Reference Design Files
File Name Description
top.sv

Top-level file containing the flat implementation of the design. This module instantiates the blinking_led sub-partition and the top_counter module.

top_counter.sv Top-level 32-bit counter that controls LED[1] directly. The registered output of the counter controls LED[0], and also powers LED[2] and LED[3] via the blinking_led module.
blinking_led.sdc

Defines the timing constraints for the project.
blinking_led.sv This module acts as the PR partition. The module receives the registered output of top_counter module, which controls LED[2] and LED[3].
blinking_led.qpf

Intel® Quartus® Prime project file containing the list of all the revisions in the project.

blinking_led.qsf

Intel® Quartus® Prime settings file containing the assignments and settings for the project.

Note:

The pr folder contains the complete set of files you create using this application note. Refer to these files at any point during the walkthrough.

Figure 2. Reference Design Files
Level Two Title