AN 953: Partially Reconfiguring a Design: on an Intel Agilex® 7 FPGA Development Board

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ID 683849
Date 1/30/2024
Public
Document Table of Contents
Document Table of Contents x
Answers to Top FAQs Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board
Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board x
Reference Design Overview Reference Design Requirements Reference Design Files Reference Design Walkthrough Document Revision History for AN 953: Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Defining Personas Step 5: Creating Revisions Step 6: Compiling the Base Revision Step 7: Preparing PR Implementation Revisions Step 8: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 8: Programming the Board x
Troubleshooting PR Programming Errors
Answers to Top FAQs
Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board

Document Revision History for AN 953: Partially Reconfiguring a Design on an Intel Agilex® 7 FPGA Development Board

Document Version Intel® Quartus® Prime Version Changes
2024.01.30 23.3
  • Added Top FAQs navigation.
  • Updated to target Intel Agilex® 7 F-Series and M-Series FPGAs.
2021.07.23 21.1
  • Initial release.
Level Two Title