AN 953: Partially Reconfiguring a Design: on an Intel® Agilex® F-Series FPGA Development Board

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ID 683849
Date 7/23/2021
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Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Agilex® F-Series FPGA Development Board
Partially Reconfiguring a Design on Intel® Agilex® F-Series FPGA Development Board x
Reference Design Overview Reference Design Requirements Reference Design Files Reference Design Walkthrough Document Revision History for AN 953: Partially Reconfiguring a Design on Intel® Agilex® F-Series FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Defining Personas Step 5: Creating Revisions Step 6: Compiling the Base Revision Step 7: Preparing PR Implementation Revisions Step 8: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 8: Programming the Board x
Troubleshooting PR Programming Errors
Partially Reconfiguring a Design on Intel® Agilex® F-Series FPGA Development Board

Troubleshooting PR Programming Errors

Ensuring proper setup of the Intel® Quartus® Prime Programmer and connected hardware helps to avoid any errors during PR programming.

If you face any PR programming errors, refer to Troubleshooting PR Programming Errors in the Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration for step-by-step troubleshooting tips.

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