Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/11/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

12. Revision History for Multi Channel DMA Intel FPGA IP for PCI Express User Guide

Date Intel® Quartus® Prime Version IP Version Changes
2023.04.11 23.1

22.2.0 [H-Tile]

5.1.0 [P-Tile]

5.1.0 [F-Tile]

2.0.0 [R-Tile]

2023.02.11 22.4

22.1.0 [H-Tile]

5.0.0 [P-Tile]

5.0.0 [F-Tile]

1.0.0 [R-Tile]

  • Initial Release and selected feature support for MCDMA R-Tile IP
  • Multi Channel DMA IP Kernel Mode Character Device Driver is no longer supported Intel Quartus Prime 22.4 release onwards. All related information has been removed.
  • Known Issues: Bullet points (3) to (7) added for Intel® Quartus® Prime 22.4 release
  • Endpoint Mode: R-Tile information added
  • Root Port Mode: F/R/P/H-Tile specific information added
  • Recommended Speed Grades: R-Tile information added. Gen5 information added.
  • Resource Utilization: BAM_BAS_MCDMA user mode information added
  • Resource Utilization: Intel Agilex R-Tile PCIe x8 [Avalon-MM Interface] table added
  • Release Information: IP version information updated. R-Tile version added.
  • Functional Description: BAM+BAS+MCDMA user mode information added
  • Endpoint MSI Support through BAS: Note added at the end of the section
  • Configuration Intercept Interface (EP Only): R-Tile information added
  • Interface Overview: R-Tile information added
  • Port List (P-Tile) (F-Tile) (R-Tile): Port List updated
  • Clocks: app_slow_clk and pcie_systempll_clk clock signals added
  • F-Tile System PLL Reference Clock Requirements: New section added
  • Resets: R-Tile reset signals added
  • Resets: i_gpio_perst#_n signal information added
  • Interface clock domain for R-Tile added for following:
    • Avalon-MM PIO Master
    • Avalon-MM Write Master (H2D)
    • Avalon-MM Read Master (D2H)
    • User Event MSI-X Interface
    • User Functional Level Reset (FLR) Interface
  • Bursting Avalon-MM Master (BAM) Interface: BAM Signals table updated
  • Bursting Avalon-MM Slave (BAS) Interface: BAS Signals table updated
  • Hard IP Reconfiguration Interface: Table updated with new signals usr_hip_reconfig_clk_o, usr_hip_reconfig_rst_n_o
  • Hard IP Reconfiguration Interface: Reconfig Address added for R-Tile
  • Configuration Intercept Interface (EP Only): R-Tile information added
  • Hard IP Status Interface: R-Tile information added
  • Hard IP Status Interface: p0_ltssm_st_hipfifo_ovrflw_o new signal added
  • MCDMA Settings: BAM+BAS+MCDMA added for User Mode parameter
  • Top-Level Settings: R-Tile information added. P-Tile and F-Tile specific information added.
  • Base Address Register: BAM+BAS+MCDMA user mode added
  • PCIe0 Configuration, Debug and Extension Options: R-Tile information added
  • PCIeo Link: New row added to the table Enable Modified TS
  • PCIeo MSI-X: New row added VF Table size to table PCIe0 PF MSI-X
  • MCDMA Settings: BAM+BAS+MCDMA added for User Mode parameter. R-Tile specific information added.
  • Example Designs: BAM+BAS+MCDMA User Mode information added. R-Tile specific information added.
  • Registers: Note added about Read/Write access to CSR address space
2022.11.01 22.3

22.0.0 [H-Tile]

4.0.0 [P-Tile]

4.0.0 [F-Tile]

  • Known Issues: Past issues that no longer present in the current release have been removed
  • Endpoint Mode: Feature list updated
  • Root Port Mode: Feature list updated
  • Release Information: IP Version and Intel® Quartus® Prime Version updated
  • Functional Description: IP Block Diagram updated
  • Multi Channel DMA: Note description updated to specify alignment in D2H direction
  • D2H Descriptor Fetch: Information added about Tail pointer updates
  • Support for Unaligned (or byte-aligned) Data Transfer: New section added
  • MSI Interrupt: New section and sub-sections added
  • 29 bit AVMM address format: New sub-section added under Config Slave (CS)
  • 14 bit AVMM address format: New sub-section added under Config Slave (CS)
  • Configuration Access Mechanism: New sub-section added under Config Slave (CS)
  • Root Port Address Translation Table Enablement: New section added
  • Port List (P-Tile) (F-Tile): Figure updated with new MSI Interface added
  • MSI Interface: New section added
  • Top-Level Settings
    • Hard IP mode parameter information updated
    • Number of PCIe parameter information updated
    • PLD Clock Frequency parameter information updated
    • Enable Independent Perst parameter information added
  • PCIe0 Configuration, Debug and Extension Options
    • Default value of parameter Gen 3 Requested equalization far-end TX preset vector for F-Tile updated
    • Default Value of parameter Gen 4 Requested equalization far-end TX preset vector for F-Tile updated
  • MCDMA Settings: New parameters added
    • Enable address byte aligned transfer
    • Enable MSI Capability
    • Enable MSI 64-bit addressing
    • Number of MSI Messages Requested
    • Enable MSI Extended Data Capability
    • Export pld_warm_rst_rdy and link_req_rst_n interface to top level
  • MCDMA Settings: New table added Root Port MCDMA Settings ATT Parameters
  • MCDMA Settings: GUI screenshot updated
  • PCIe1 Settings: New section added
  • Example Designs
    • Information updated for Current development kit parameter
    • GUI screenshot added Example Design Settings [for x16 mode]
    • GUI screenshot added Example Design Settings [for 2x8 mode]
  • Queue Control (QCSR)
    • Table Queue Control Registers: Register Name Q_DEBUG_STATUS_3 information removed
    • Table Queue Control Registers: Register Name Q_DATA_DRP_ERR_CTR information added
    • New register table Q_DATA_DRP_ERR_CTR (Offset 8’h40) added
Troubleshooting/Debugging Chapter updates
  • Unless or otherwise noted, the debug toolkit features described in the Troubleshooting/Debugging Chapter apply to both P-Tile and F-Tile.
  • Enabling the Debug Toolkit: Description of this operation expanded
  • Launching the Debug Toolkit: New note added for about the standalone install of Intel® Quartus® Prime Pro Edition
  • Main View: Channel Mapping for Bifurcated Ports table updated
  • Toolkit Parameters
    • In table Available Parameter Settings, rows Advertised speed, Advertised width, Negotiated speed, Negotiated width have been updated
    • In table Available Parameter Settings, new row PIPE PhyStatus (For F-Tile debug toolkit only) has been added
  • Channel Parameters: Tag (For P-Tile debug toolkit only) has been added wherever required
  • Eye Viewer: F-Tile support information added
  • Link Inspector: New section added
2022.08.19 22.2

21.5.0 [H-Tile]

3.1.0 [P-Tile]

3.0.0 [F-Tile]

  • Release Information: Table updated
  • Functional Description: Block Diagram updated
  • MCDMA Settings: Number of ports parameter info updated
  • Top-Level Settings: Enable Ptile Debug Toolkit (P-Tile) and Enable Debug Toolkit (F-Tile) parameters row added
  • Multifunction and SR-IOV System Settings Paramters [Endpoint Mode: Number of DMA channels allocated to PF0 parameter info updated
  • Example Designs: Currently Selected Example Design parameter info updated for H-Tile
  • Example Designs: Current development kit parameter info updated for P-Tile and F-Tile
  • Eye Viewer: Note added about eye-margining
4 Port AVST Mode has been deprecated from this release. All related 4 Port Mode information has been removed from the following sections:
  • Endpoint Mode
  • Avalon-ST Source (H2D) and Sink (D2H)
  • Packet (File) Boundary
  • Bursting Avalon-MM Slave (BAS)
  • Avalon-ST Source (H2D)
  • Avalon-ST Sink (D2H)
  • Port List (H-Tile)
  • Port List (P-Tile and F-Tile)
2022.04.20 22.1

21.4.0 [H-Tile]

3.0.0 [P-Tile]

2.0.0 [F-Tile]

  • Known Issues [New section added]
  • Release Information [IP Version updated]
  • Recommended Speed Grades [Table updated]
  • Resource Utilization [All tables updated]
  • Descriptors [Software Descriptor Format Table Rows Updated: SRC_ADDR [63:0], DEST_ADDR [127:64], PYLD_CNT [147:128]]
  • Avalon-MM PIO Master [Description updated]
  • Avalon-ST 1-Port Mode [Note added]
  • Bursting Avalon-MM Master [Description updated]
  • H2D Descriptor Format (h2ddm_desc) [Table Rows Updated: RSVD [200:200], RSVD [216:201]]
  • H2D Descriptor Completion Packet Format (h2ddm_desc_cmpl) [Table Rows Updated: En_partial_cmpl_data [82:82], Completion data]
  • D2H Data Mover [Table Row updated: d2hdm_desc]
  • D2H Descriptor Format (d2hdm_desc) [Table Rows updated: SRC_ADDR [63:0], MM_mode [176:176], App_specific_bits [179:177], DESC_IDX1 [195:180], RSVD [196:196], RSVD [212:197]]
  • Application Specific Bits [Table updated]
  • Avalon-MM PIO Master [Note added]
  • Avalon-MM PIO Master [Table updated. Row: rx_pio_address_o[n:0]]
  • MCDMA Settings [H-Tile. New GUI Screesnhot added] [D2H Prefetch channels Row in table updated]
  • Base Address Register [P-Tile and F-Tile] [Note added]
  • MCDMA Settings [P-Tile and F-Tile] [D2H Prefetch channels Row in table updated]
  • Example Designs [Currently Selected Example Design Row in Table updated]
  • Software Flow [QCSR Registers list updated in Step 1]
  • Queue Control (QCSR) [Queue Control Registers Table Rows Updated: Q_PYLD_CNT,Q_RESET]
  • Control Register (GCSR) [Note Added]
2022.01.14 21.4

21.3.0 [H-Tile]

2.2.0 [P-Tile]

1.1.0 [F-Tile]

  • Data Mover Only user mode option added to Endpoint Mode
  • Resource Utilization tables updated
  • IP Version updated in Release Information
  • Data Mover Only user mode option added in Chapter Functional Description
  • Data Mover Interface and Hard IP Status Interface added to Chapter Interface Iverview
  • Port List (P-Tile and F-Tile) figure updated with data mover mode interfaces
  • PCIe0 Configuration, Debug and Extension Options section updated in Parameters (P-Tile and F-Tile) Chapter
  • Enable 10-bit tag support GUI feature added to MCDMA Settings in Parameters (P-Tile and F-Tile) Chapter
  • Data Mover Only user mode option added to Example Designs table in Parameters (P-Tile and F-Tile) Chapter
  • Device Management and Channel Management sections updated for Network Device Driver
  • ethtool support and debugfs support added to Network Device Driver
  • SRIOV Support information added for Network Device Driver
2021.10.29 21.3

21.2.0 [H-Tile]

2.1.0 [P-Tile]

1.0.0 [F-Tile]

  • Recommended Speed Grades table updated with F-Tile support information
  • Resource Utilization tables updated
  • Release Information updated
  • Valid user modes and required functional blocks table updated
  • Address format information added to Config Slave
  • Multi Channel DMA IP for PCI Express Port List (P-Tile and F-Tile) figure updated with F-Tile information
  • Config TL Interface signal table updated
  • F-Tile support information added to Configuration Intercept Interface (EP Only)
  • F-Tile support information added to Parameters (P-Tile and F-Tile) Chapter
  • MCDMA IP Software Driver Differentiation table added
  • Network Device Driver information added in Multi Channel DMA IP Kernel Mode Network Device Driver
  • Debug Toolkit information added
2021.08.16 21.2

21.1.0 [H-Tile]

2.0.0 [P-Tile]

  • Fixed H-Tile IP revision number
  • Added 500 MHz support for P-Tile MCDMA IP
  • Added P-Tile single port Avalon-ST DMA up to 256 channels
  • Added MCDMA IP DPDK Poll-Mode based Driver
  • Added MCDMA IP Kernel Mode (No SRIOV) Driver
2021.05.28 21.1

2.0.0 [H-Tile]

1.0.0 [P-Tile]

  • PCIe Gen4 (P-Tile) Support
  • Support for x8 link width
  • MCDMA 1 port AVST interface
  • BAM, BAS, BAM+BAS, BAM+MCDMA modes
  • SR-IOV support
  • Root Port support (IP only)
  • Config Slave interface for RP
2020.07.20 20.2

20.0.0 [H-Tile]

Initial Release