Hybrid Memory Cube Controller Design Example User Guide

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ID 683817
Date 5/02/2016
Public
Document Table of Contents
Document Table of Contents x
1. Hybrid Memory Cube Controller Design Example Quick Start Guide 2. Hybrid Memory Cube Controller Design Example Description A. Additional Information
1. Hybrid Memory Cube Controller Design Example Quick Start Guide x
1.1. Design Example Directory Structure 1.2. Design Example Components 1.3. Generating the Design Example 1.4. Understanding the Testbench 1.5. Simulating the Design Example Testbench 1.6. Setting Up the Board 1.7. Compiling and Testing the Design Example in Hardware
2. Hybrid Memory Cube Controller Design Example Description x
2.1. Design Example Description 2.2. Features 2.3. Hardware and Software Requirements 2.4. Functional Description 2.5. Interface Signals 2.6. Design Example Register Map
A. Additional Information x
A.1. HMC Controller Design Example User Guide Revision History A.2. How to Contact Intel A.3. Typographic Conventions
1. Hybrid Memory Cube Controller Design Example Quick Start Guide
2. Hybrid Memory Cube Controller Design Example Description
A. Additional Information

1.3. Generating the Design Example

Figure 4. Procedure
Figure 5. Example Design Tab in Hybrid Memory Cube Controller Parameter Editor

Follow these steps to generate the Arria 10 hardware design example and testbench:

  1. In the IP Catalog (Tools > IP Catalog), select the Arria 10 target device family.
  2. In the IP Catalog, locate and select Hybrid Memory Cube Controller. The New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .qsys .
  4. You must select a specific Arria 10 device in the Device field, or keep the default device the Quartus Prime software selects.
  5. Click OK. The IP parameter editor appears.
  6. On the IP tab, specify the parameters for your IP core variation.
  7. On the Example Design tab, choose the following settings for the design example:
    1. For Select Design, select the HMCC Daughter Board option.
    2. For Example Design Files, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware design example.
    3. For Generated HDL Format, only Verilog is available.
    4. For Target Development Kit select the Arria 10 GX FPGA Development Kit (Production Silicon).
      Note:

      When you choose this kit, the hardware design example overwrites your previous device selection with the device on the target board.

      When you generate the design example, the Intel® Quartus® Prime software creates Intel® Quartus® Prime project, setting, and pin assignments for the board you selected. If you do not want the software to target a specific board, select None.

  8. Click the Generate Example Design button.
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