Hybrid Memory Cube Controller Design Example User Guide

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ID 683817
Date 5/02/2016
Public
Document Table of Contents
Document Table of Contents x
1. Hybrid Memory Cube Controller Design Example Quick Start Guide 2. Hybrid Memory Cube Controller Design Example Description A. Additional Information
1. Hybrid Memory Cube Controller Design Example Quick Start Guide x
1.1. Design Example Directory Structure 1.2. Design Example Components 1.3. Generating the Design Example 1.4. Understanding the Testbench 1.5. Simulating the Design Example Testbench 1.6. Setting Up the Board 1.7. Compiling and Testing the Design Example in Hardware
2. Hybrid Memory Cube Controller Design Example Description x
2.1. Design Example Description 2.2. Features 2.3. Hardware and Software Requirements 2.4. Functional Description 2.5. Interface Signals 2.6. Design Example Register Map
A. Additional Information x
A.1. HMC Controller Design Example User Guide Revision History A.2. How to Contact Intel A.3. Typographic Conventions
1. Hybrid Memory Cube Controller Design Example Quick Start Guide
2. Hybrid Memory Cube Controller Design Example Description
A. Additional Information

1.6. Setting Up the Board

Set up the board to run the hardware design example.
Note: Ensure that power is turned off before you change any settings.
  1. Set the DIP switches on the daughter card as follows: Set DIP switch SW1 to indicate cube ID 0:
    Switch Function Setting
    1 CUB[0] Open
    2 CUB[1] Open
    3 CUB[2] Open
    4 — Don't Care
    Set DIP switch SW2 to specify clock settings:
    Switch Function Setting
    1 CLK1_FSEL0 Open (125 MHz)
    2 CLK1_FSEL1 Open (125 MHz)
    3 CLK1_SEL Open (Crystal)
    4 — Don't Care
  2. Connect the HMC daughter card to the Arria 10 FPGA Development Kit using the daughter card's J8 and J10 connectors.
  3. Set the jumpers on the Arria 10 GX FPGA Development Kit:
    • Add shunts to the J8 jumper to select 1.5 V as the VCCIO setting for FMC connector B.
    • Add shunts to the J11 jumper to select 1.8 V as the VCCIO setting for FMC connector A.
    Figure 7. Arria 10 GX FPGA Development Kit and HMC Daughter Card
Level Two Title