F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 1/30/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Generating Tile Files 1.4. Simulating the Design Example Testbench 1.5. Hardware and Software Requirements 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.8. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.4. Simulating the Design Example Testbench x
1.4.1. Fast Sim Model for FGT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1.7. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example

After you compile the F-Tile Ethernet Intel FPGA Hard IP core design example and configure it on your Intel® Agilex™ device, you can use the System Console to program the IP core.

Follow these steps to test the hardware design example on the System Console:
  1. Navigate to the hardware directory: <design_example>/hardware_test_design/hwtest.
  2. Open Tools > System Debugging Tools > System Console or type command:
    system-console &
  3. Run the following commands in the System Console Tcl shell. 
    source main_<Ethernet_rate>.tcl
set_jtag<number_of appropriate_JTAG_master>
    Note: The set_jtag command places the Intel® Agilex™ device on the JTAG chain.
    Note: If you enabled auto-negotiation and link training in your design, follow the hardware design example steps described in Hardware Design Example.
  4. Run one of the following commands.
    • If you use the internal serial loopback, enter 
      run_test
    • If you inserted an external loopback plug into the desired Ethernet port, enter 
      run_test_without_loopback
The hardware design example uses run_test command to initiate packet transmission from packet generator to the IP core. Specifically, the script performs the following steps:
  • chkphy_status: Displays the clock frequencies and PMA PHY lock status.
  • chkmac_status: Displays the MAC statistics counters.
  • clear_all_stats: Clears the IP core statistics counters.
  • start_pkt_gen: Starts the packet generator.
  • stop_pkt_gen: Stops the packet generator.
  • internal_loop_back_bk no_of_lanes: Enables the internal loop back for FHT variant.
  • internal_loop_back_ux no_of_lanes: Enables the internal loop back for FGT variant.
The following sample output illustrates a successful hardware test run: 
% run_test_without_loopback
--- Turning off packet generation ----
--------------------------------------
--- Wait for RX clock to settle... ---
--------------------------------------
-------- Printing PHY status ---------
--------------------------------------
 RX PHY Register Access: Checking Clock Frequencies (KHz) 
	TXCLK 		:41505  (KHZ) 
	RXCLK 		:41503  (KHZ) 

 TX PLL Lock Status           0x000000ff
 RX Frequency Lock Status     0x000000ff
 RX PCS Ready                 0x00000001
 TX Lanes Stable              0x00000001
 Deskew status                0x00000001 
 Link Fault Status            0x00000000
 RX Frame Error               0x00000000
 RX AM LOCK Condition         0x00000001 

---- Clearing MAC stats counters -----
---- Initialize PKT ROM Read address for IP_INST[0] ----
--------------------------------------
--------- Sending packets... ---------
--------------------------------------
----- Reading MAC stats counters -----
--------------------------------------

==========================================================================================
                        STATISTICS FOR BASE 20480 (Rx)                               
 ==========================================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0 
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 0 
65 - 127 Byte Frames             : 16 
128 - 255 Byte Frames            : 0 
256 - 511 Byte Frames            : 0 
512 - 1023 Byte Frames           : 0 
1024 - 1518 Byte Frames          : 0 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 0 
Rx Frame Starts                  : 16
Multicast data  OK  Frame        : 16
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 0
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0
Data and padding octets          : 800
Frame octets:                    : 1088
==========================================================================================
                        STATISTICS FOR BASE 20480 (Tx)                               
 ==========================================================================================
Fragmented Frames                : 0 
Jabbered Frames                  : 0 
Any Size with FCS Err Frame      : 0
Right Size with FCS Err Fra      : 0 
Multicast data  Err Frames       : 0 
Broadcast data Err  Frames       : 0 
Unicast data Err  Frames         : 0 
Multicast control  Err Frame     : 0 
Broadcast control Err  Frame     : 0 
Unicast control Err  Frames      : 0 
Pause control Err  Frames        : 0 
64 Byte Frames                   : 0
65 - 127 Byte Frames             : 16
128 - 255 Byte Frames            : 0 
256 - 511 Byte Frames            : 0 
512 - 1023 Byte Frames           : 0 
1024 - 1518 Byte Frames          : 0 
1519 - MAX Byte Frames           : 0 
> MAX Byte Frames                : 0 
Tx Frame Starts                  : 16 
Multicast data  OK  Frame        : 16
Broadcast data OK   Frame        : 0 
Unicast data OK   Frames         : 0 
Multicast Control Frames         : 0 
Broadcast Control Frames         : 0 
Unicast Control Frames           : 0 
Pause Control Frames             : 0
Data and padding octets          : 800
Frame octets:                    : 1088
------------ Done ---------------------
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