F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 1/30/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Generating Tile Files 1.4. Simulating the Design Example Testbench 1.5. Hardware and Software Requirements 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.8. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.4. Simulating the Design Example Testbench x
1.4.1. Fast Sim Model for FGT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

5.1. Features

  • Supports multiple instantiations of the same F-Tile Ethernet Intel FPGA Hard IP. For more information, refer to the Available Number of Multiple IP Instances per Ethernet Mode table.
  • Each instance supports 10G, 25G, 40G, 50G, 100G, 200G, and 400G Ethernet rates
  • Each instance supports Avalon® streaming interface for 10G, 25G, 40G, 50G, and 100G Ethernet rates with synchronized or asynchronous adapter
  • Each instance supports MAC segmented interface
  • Instantiates F-Tile Reference and System PLL Clocks Intel® FPGA IP based on Ethernet configuration
When you enable the multi instance IP option, the design example generates multiple instances of the same IP. The table specifies the number of instantiated F-Tile Ethernet Intel FPGA Hard IPs per Ethernet mode.
Table 13.  Available Number of Multiple IP Instances per Ethernet Mode
Ethernet Mode Modulation PMA Type Number of Multiple IP Instances
10GE-1 NRZ FGT 16
25GE-1 NRZ FGT 16
25GE-1 NRZ FHT 4
40GE-4 NRZ FGT 4
50GE-2 NRZ FGT 8
50GE-2 NRZ FHT 2
50GE-1 PAM4 FGT 8
50GE-1 PAM4 FHT 4
100GE-4 NRZ FGT 4
100GE-4 NRZ FHT 1
100GE-2 NRZ FGT 4
100GE-2 NRZ FHT 2
100GE-1 PAM4 FHT 4
200GE-8 NRZ FGT 2
200GE-4 PAM4 FGT 2
200GE-4 PAM4 FHT 1
200GE-2 PAM4 FHT 2
400GE-8 PAM4 FGT 1
400GE-4 PAM4 FHT 1
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