F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 1/30/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Generating Tile Files 1.4. Simulating the Design Example Testbench 1.5. Hardware and Software Requirements 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.8. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.4. Simulating the Design Example Testbench x
1.4.1. Fast Sim Model for FGT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1.2. Directory Structure

The F-Tile Ethernet Intel FPGA Hard IP core design example file directories contain the following generated files for the design example.
Figure 6. Directory Structure for F-Tile Ethernet Intel FPGA Hard IP Design ExampleThe <ethernet_mode> refers to the selected Ethernet mode in the IP tab of the IP parameter editor.
Table 1.  Directory and File Description
Directory/File Description
<design_example_dir>/hardware_test_design/eth_f_hw.qpf Intel® Quartus® Prime project file.
<design_example_dir>/hardware_test_design/eth_f_hw.qsf Intel® Quartus® Prime setting file.
<design_example_dir>/hardware_test_design/eth_f_hw.v Design example top-level HDL.
<design_example_dir>/hardware_test_design/eth_f_hw.sdc Synopsys Design Constraints (SDC) file.
<design_example_dir>/hardware_test_design/common Hardware design example support files.
<design_example_dir>/hardware_test_design/hwtest/main.tcl Main file for accessing System Console.
The Intel® Quartus® Prime software generates the design example files in the following folders:
  • <design_example_dir>/ex_<ethernet_rate>G: IP core files
  • <design_example_dir>/example_testbench: simulation files for testbench
  • <design_example_dir>/hardware_test_design: hardware test design files
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