AN 809: SerialLite III IP Core Feature and Interface Differences between Stratix 10, Arria 10, and Stratix V

ID 683797
Date 6/19/2017
Public

Clocking

Table 4.  TX PLL Differences between Stratix® 10, Arria® 10, and Stratix® V Devices
Stratix® 10 Arria® 10 Stratix® V Comments
User shall instantiate a TX PLL outside the IP core User shall instantiate a TX PLL outside the IP core IP core includes a TX PLL TX PLL (ATX, CMU, or fPLL) instantiation requirement
Table 5.  Standard Clocking Mode Differences between Stratix® 10, Arria® 10, and Stratix® V Devices
Stratix® 10 Arria® 10 Stratix® V Comments
User logic shall provide a user_clock to the IP core IP core provides a user_clock to user logic IP core provides a user_clock to user logic

User clock direction.

Specify frequency in the IP parameter GUI.

External PLL instantiated by user provides the user_clock An IOPLL inside the IP core generates the user_clock An fPLL inside the IP core generates the user_clock User clock generation.

User clock PLL (fPLL or IOPLL) sharing supported across multiple IP core instances

User clock PLL (IOPLL) cannot be automatically shared across multiple IP core instances User clock PLL (fPLL) cannot be automatically shared across multiple IP core instances PLL sharing for user clock.

For Stratix® 10, user clock PLL is external to the IP core.

For Arria® 10 and Stratix® V, the user clock PLL is in the IP core.

Figure 1.  Stratix® 10 Standard Clocking Mode Clocking
Figure 2.  Arria® 10 Standard Clocking Mode Clocking
Figure 3.  Stratix® V Standard Clocking Mode Clocking
Table 6.  Advanced Clocking Mode Differences between Stratix® 10, Arria® 10, and Stratix® V devices
Stratix® 10 Arria® 10 Stratix® V Comments
Lane data rate divided by PCS-PMA bus width (PCS-PMA bus width: 64)

Lane data rate divided by PCS-PMA bus width (PCS-PMA bus width: 64)

Lane data rate divided by PCS-PMA bus width (PCS-PMA bus width: 40) Sink Interface clock frequency.
Note: Source user clock frequency is specified in the IP Core GUI if User input selects User Clock Frequency.
Figure 4.  Stratix® 10 and Arria® 10 Advanced Clock Mode Clocking
Figure 5.  Stratix® V Advanced Clock Mode Clocking