IP Core GUI
Stratix® 10 | Arria® 10 | Stratix® V | Comments |
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Adaptation FIFO partial full threshold | N/A | N/A | Stratix® 10: Backpressure the upstream data through tx_ready port when the partial full flag triggers. |
N/A | N/A | Device speed grade | Transceiver speed grade. Stratix® 10 and Arria® 10: N/A (user should refer to the transceiver PHY datasheet for the maximum data rate supported.) Stratix® V: This is used to determine supported data rate ( Stratix® V IP parameter does not generate an error) |
N/A | N/A | PLL type (CMU, ATX, fPLL) | Stratix® 10 and Arria® 10: Transmitter (TX) PLL is instantiated outside the IP core. |
Example Design Presets | |||
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Presets in IP GUI supported for design example generation. |