AN 872: Thermal and Power Guidelines: For Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683795
Date 8/30/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Using the Board Management Controller 3. AFU Design Power Verification 4. Document Revision History for Thermal and Power Guidelines for Intel PAC with Intel Arria 10 GX FPGA
1. Introduction x
1.1. About this Document 1.2. Power Specification 1.3. Prerequisites 1.4. Tools Requirements
2. Using the Board Management Controller x
2.1. Auto-Shutdown 2.2. Recovering After Auto-Shutdown 2.3. Monitor On-Board Sensors Using OPAE 2.4. Monitor On-Board Sensors Using BWMonitor
3. AFU Design Power Verification x
3.1. Power Measurement Flow 3.2. Measuring the Total Board Power 3.3. Measuring the Real Static Power 3.4. Estimating the Worst Case Core Static Power
3.3. Measuring the Real Static Power x
3.3.1. Using the Intel® Quartus® Prime Programmer
1. Introduction
2. Using the Board Management Controller
3. AFU Design Power Verification
4. Document Revision History for Thermal and Power Guidelines for Intel PAC with Intel Arria 10 GX FPGA

2.2. Recovering After Auto-Shutdown

The Board Management Controller holds power off until the next power cycle. Therefore, when an Intel® FPGA PAC card power is shut down, you must power cycle the server to return power to the Intel® FPGA PAC.

The common cause of power shutdown is the FPGA overheating (when the core temperature is over 100°C), or the FPGA drawing excessive current. This typically happens when the AFU design exceeds the Intel® FPGA PAC defined power envelopes or there is insufficient airflow. In this case, you must reduce power consumption in your AFU.

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