AN 872: Thermal and Power Guidelines: For Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683795
Date 8/30/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Using the Board Management Controller 3. AFU Design Power Verification 4. Document Revision History for Thermal and Power Guidelines for Intel PAC with Intel Arria 10 GX FPGA
1. Introduction x
1.1. About this Document 1.2. Power Specification 1.3. Prerequisites 1.4. Tools Requirements
2. Using the Board Management Controller x
2.1. Auto-Shutdown 2.2. Recovering After Auto-Shutdown 2.3. Monitor On-Board Sensors Using OPAE 2.4. Monitor On-Board Sensors Using BWMonitor
3. AFU Design Power Verification x
3.1. Power Measurement Flow 3.2. Measuring the Total Board Power 3.3. Measuring the Real Static Power 3.4. Estimating the Worst Case Core Static Power
3.3. Measuring the Real Static Power x
3.3.1. Using the Intel® Quartus® Prime Programmer
1. Introduction
2. Using the Board Management Controller
3. AFU Design Power Verification
4. Document Revision History for Thermal and Power Guidelines for Intel PAC with Intel Arria 10 GX FPGA

3.2. Measuring the Total Board Power

Follow these steps:
  1. Install the Intel® PAC with Intel® Arria® 10 GX FPGA into a qualified PCIe slot in the server. If you are using BWMonitor for measurement, connect the Micro-USB cable from back of the card to any USB port of the server.
  2. Load your AFU and run at its maximum power.
    1. If the AFU uses Ethernet, then ensure that the network cable or module is inserted and connected to the link partner and network traffic is turned on in the AFU.
    2. If appropriate, run DMA continuously to exercise on-board DDR4.
    3. Run your applications on the host to feed the AFU the worst-case traffic as well as to fully exercise FPGA. Ensure that you stress the FPGA with the most stressful data traffic.
    Run this step for minimum 15 minutes to allow the FPGA core temperature to settle.
    Note: During testing, monitor the total board power, FPGA power, and FPGA core temperature value to ensure they stay within specification. If 66 W, 45 W, or 100°C limits are reached, stop the test immediately.
  3. After the FPGA core temperature becomes stable, use the fpgainfo program or BWMonitor tool to record the total board power and FPGA core temperature. Input these values in row Step 1: Total board power measurement of the Intel® FPGA PAC Power Estimator Sheet.
    Figure 2.  Intel® FPGA PAC Power Estimator Sheet Sample
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