Intel® Cyclone 10 Native Floating-Point DSP FPGA IP User Guide

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ID 683789
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP User Guide 2. Document Revision History
1. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP User Guide x
1.1. Parameterizing the Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP 1.2. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP Parameters 1.3. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP Signals
1. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP User Guide
2. Document Revision History

1.1. Parameterizing the Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP

Select different parameters to create an IP core suitable for your design.
  1. In Intel® Quartus® Prime Pro Edition,create a new project that targets a Intel® Cyclone® 10 GX device.
  2. In IP Catalog, click on Library > DSP > Primitive DSP > Intel® Cyclone® 10 GX Native Floating Point DSP.
    The Intel® Cyclone® 10 GX Native Floating-Point DSP IP Core IP parameter editor opens.
  3. In the New IP Variation dialog box, enter an Entity Name and click OK.
  4. Under Parameters, select the DSP Template and the View you want for your IP core
  5. In the DSP Block View, toggle the clock or reset of each valid register.
  6. For Multiply Add or Vector Mode 1, click on the Chain In multiplexer in the GUI to select input from chainin port or Ax port.
  7. Click the Adder symbol in the GUI to select addition or subtraction.
  8. Click on the Chain Out multiplexer in the GUI to enable chainout port.
  9. Click Generate HDL.
  10. Click Finish.
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