Intel® Cyclone 10 Native Floating-Point DSP FPGA IP User Guide

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ID 683789
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP User Guide 2. Document Revision History
1. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP User Guide x
1.1. Parameterizing the Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP 1.2. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP Parameters 1.3. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP Signals
1. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP User Guide
2. Document Revision History

1.3. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP Signals

Figure 2.  Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP Signals

The figure shows the input and output signals of the IP core.

Table 3.   Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP Input Signals
Signal Name Type Width Default Description
ax[31:0] Input 32 Low Input data bus to the multiplier.
Available in:
  • Add mode
  • Multiply-Add mode without chainin and chainout feature
  • Vector Mode 1
  • Vector Mode 2
ay[31:0] Input 32 Low Input data bus to the multiplier.

Available in all floating-point operational modes.

az[31:0] Input 32 Low

Input data bus to the multiplier.

Available in:
  • Multiply
  • Multiply Add
  • Multiply Accumulate
  • Vector Mode 1
  • Vector Mode 2
chainin[31:0] Input 32 Low

Connect these signals to the chainout signals from the preceding floating-point DSP IP core.

clk[2:0] Input 3 Low Input clock signals for all registers.

These clock signals are only available if any of the input registers, pipeline registers, or output register is set to Clock0 or Clock1 or Clock2.

ena[2:0] Input 3 High Clock enable for clk[2:0].

These signals are active-High.

  • ena[0] is for Clock0
  • ena[1] is for Clock1
  • ena[2] is for Clock2
aclr[1:0] Input 2 Low

Asynchronous clear input signals for all registers.

These signals are active-high.

Use aclr[0] for all input registers and use aclr[1] for all pipeline and output registers.

accumulate Input 1 Low Input signal to enable or disable the accumulator feature.
  • Assert this signal to enable feedback the adder's output.
  • De-assert this signal to disable the feedback mechanism.

You can assert or de-assert this signal during run-time.

Available in Multiply Accumulate mode.

chainout[31:0] Output 32 — Connect these signals to the chainin signals of the next floating-point DSP IP core.
result[31:0] Output 32 — Output data bus from IP core.
Level Two Title