Intel® Cyclone 10 Native Floating-Point DSP FPGA IP User Guide

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ID 683789
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP User Guide 2. Document Revision History
1. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP User Guide x
1.1. Parameterizing the Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP 1.2. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP Parameters 1.3. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP Signals
1. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP User Guide
2. Document Revision History

1.2. Intel® Cyclone® 10 GX Native Floating-Point DSP Intel® FPGA IP Parameters

Table 1.  Parameters
Parameter Value Default Value Description
DSP Template

Multiply

Add

Multiply Add

Multiply Accumulate

Vector Mode 1

Vector Mode 2

Multiply

Select the desired operational mode for the DSP block.

The selected operation is reflected in the DSP Block View.

View

Register Enables

Register Clears

Register Enables

Options to select clocking scheme or reset scheme for registers view. The selected operation is reflected in the DSP Block View.

Select Register Enables for DSP Block View to show registers clocking scheme. You can change the clocks for each of the registers in this view.

Select Register Clears for DSP Block View to show registers reset scheme. Turn on Use Single Clear to change the registers reset scheme.

Use Single Clear On or off Off

Turn on this parameter if you want a single reset to reset all the registers in the DSP block. Turn off this parameter to use different reset ports to reset the registers.

Turn on for clear 0 on output register; turn off for clear 1 on output register.

Clear 0 for input registers uses aclr[0] signal.

Clear 1 for output and pipeline registers uses aclr[1] signal.

All input registers use aclr[0] reset signal. All output and pipeline registers use aclr[1] reset signal.

DSP View Block.
Chain In Multiplexer (14)

Enable

Disable

 Disable

Click on the multiplexer to enable chainin port.

Chain Out Multiplexer (12)

Disable

Enable

 Disable

Click on the multiplexer to enable chainout port.

Adder (13)

+

-

+

Click on the Adder symbol to select addition or subtraction mode.

Register Clock
  • ax_clock (2)
  • ay_clock (3)
  • az_clock (4)
  • mult_pipeline_clock(5)
  • ax_chainin_pl_clock (7)
  • adder_input_clock (9)
  • adder_input_2_clock (10)
  • output_clock (11)
  • accumulate_clock (1)
  • accum_pipeline_clock (6)
  • accum_adder_clock (8)

None

Clock 0

Clock 1

Clock 2

Clock 0

To bypass any register, toggle the register clock to None.

Toggle the register clock to:
  • Clock 0 to use clk[0] signal as the clock source
  • Clock 1 to use clk[1] signal as the clock source
  • Clock 2 to use clk[2] signal as the clock source

You can only change these settings when you select Register Enables in View parameter.

Figure 1. DSP Block View
Table 2.  DSP Templates
DSP Templates Description
Multiply

Performs single precision multiplication operation and applies the following equation:

  • Out = Ay * Az
Add Performs single precision addition or subtraction operation and applies the following equations:.
  • Out = Ay + Ax
  • Out = Ay - Ax
Multiply Add

This mode performs single precision multiplication, followed by addition or subtraction operations and applies the following equations.

  • Out = (Ay * Az) - chainin
  • Out = (Ay * Az) + chainin
  • Out = (Ay * Az) - Ax
  • Out = (Ay * Az) + Ax
Multiply Accumulate

Performs floating-point multiplication followed by floating-point addition or subtraction with the previous multiplication result and applies the following equations:

  • Out(t) = [Ay(t) * Az(t)] - Out (t-1) when accumulate signal is driven high.
  • Out(t) = [Ay(t) * Az(t)] + Out (t-1) when accumulate port is driven high.
  • Out(t) = Ay(t) * Az(t) when accumulate port is driven low.
Vector Mode 1

Performs floating-point multiplication followed by floating-point addition or subtraction with the chainin input from the previous variable DSP block and applies the following equations:.

  • Out = (Ay * Az) - chainin
  • Out = (Ay * Az) + chainin
  • Out = (Ay * Az) , chainout = Ax
Vector Mode 2 Performs floating-point multiplication where the IP core feeds the multiplication result is directly to chainout. The IP core then adds or subtracts the chainin input from the previous variable DSP block from input Ax as the output result.

This mode applies the following equations:

  • Out = Ax - chainin , chainout = Ay * Az
  • Out = Ax + chainin , chainout = Ay * Az
  • Out = Ax , chainout = Ay * Az
Level Two Title