Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

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ID 683763
Date 5/24/2022
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Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices 7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations
1.3.1. CvP Limitations x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes 2.3. Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe Wake-Up Time Requirement
4.1.2. PCIe Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel® Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe* Express 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing Open Source CvP Driver in Linux Systems 6.1.5.2. Setting Up the Correct MSEL Switch State 6.1.5.3. Programming CvP Images
6.1.5.1. Installing Open Source CvP Driver in Linux Systems x
6.1.5.1.1. Downstream open source CvP Driver 6.1.5.1.2. Upstream open source CvP Driver
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting Up the Base Revision 6.2.4. Setting Up and Compile the Updated Revision 6.2.5. Converting the SOF File 6.2.6. Programming the Core RBF file from the Updated Revision via PCIe Link
6.2.3. Setting Up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices
7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

6.1.1. Generating the Synthesis HDL files for Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe* Express

Follow these steps to generate the synthesis HDL files with CvP enabled:

  1. Open the Intel® Quartus® Prime Pro Edition software.
  2. On the Tools menu, click Platform Designer . The Open System window appears.
  3. For System, click + and specify a File Name to create a new platform designer system. Click Create.
  4. On the System Contents tab, delete the clock_in and reset_in components that appear by default.
  5. In the IP Catalog locate and double-click Intel P-tile Avalon-ST for PCI Express. The new window appears.
  6. On the IP Settings tab, specify the parameters and options for your design variation.
  7. On the Top-Level Settings tab, select the Enable CVP (Intel VSEC) option.
    Note: For R-Tile Avalon-ST for PCI Express, on the Top-Level Settings tab, select the Enable CVP (Intel VSEC) option.
    Note: For F-Tile Avalon-ST for PCI Express, on the PCIe0 Settings -> PCIe0 PCI Express/ PCI Capabilities -> PCIe0 VSEC tab, select the Enable CVP (Intel VSEC) option.
    Note: For devices that support two PCIe Hard IP block on the left, CvP application can use either one of the two PCIe Hard IP blocks on left side. This option is to enable the CvP application to either lower or upper PCIe Hard block. Subsequently, you must do the pin assignments properly to use either lower or upper PCIe Hard block for CvP application.
  8. On the Example Designs tab, select the Simulation option to generate the testbench, and select the Synthesis option to generate the hardware design example.
  9. For Generated file format, only Verilog is available.
  10. Click the Generate Example Design button. The Select Example Design Directory dialog box appears. Click OK. The software generates Intel® Quartus® Prime project files for PCI Express reference design. Click Close when generation completes. An example design intel_pcie_ptile_ast_0_example_design is created in your project directory.
  11. Click Finish. Close your current project and open the generated PCI Express example design (pcie_ed.qpf).
  12. Complete your CvP design by adding any desired top-level design and any other required modules. You must ensure you do the pin assignments properly to use either lower or upper PCIe Hard block for CvP application.
    Note: Reference design for CvP initialization and update is not available in the current version of the Intel® Quartus® Prime software.
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