Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

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ID 683763
Date 5/24/2022
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Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices 7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations
1.3.1. CvP Limitations x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes 2.3. Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe Wake-Up Time Requirement
4.1.2. PCIe Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel® Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe* Express 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing Open Source CvP Driver in Linux Systems 6.1.5.2. Setting Up the Correct MSEL Switch State 6.1.5.3. Programming CvP Images
6.1.5.1. Installing Open Source CvP Driver in Linux Systems x
6.1.5.1.1. Downstream open source CvP Driver 6.1.5.1.2. Upstream open source CvP Driver
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting Up the Base Revision 6.2.4. Setting Up and Compile the Updated Revision 6.2.5. Converting the SOF File 6.2.6. Programming the Core RBF file from the Updated Revision via PCIe Link
6.2.3. Setting Up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices
7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

6.2.3.2. Defining a Logic Lock Region

You can reserve the core resources in an updated revision for the reserved core partition by defining a fixed size and location, core-only, and reserved logic lock region. The updated revision uses this area for core development, and the area can contain only the core logic. Ensure the reserved placement region size is large enough to contain all core logic in the updated revision.

Follow these steps to define a logic lock region for core base revision:

  1. In the Project Navigator window, right-click the design instance and click Logic Lock Region > Create New Logic Lock Region. The new region appears in the Logic Lock Regions window. You can also verify the region by right-click the design instance and click Locate Node > Locate in Chip Planner.
    Figure 17. Creating Logic Lock Region from Project Navigator
  2. Click Assignments > Logic Lock Regions Window, to display the Logic Lock Regions window.
    1. Specify Width, Height, and the placement region co-ordinates in the Origin column.
    2. Enable the Reserved and Core-Only options.
    3. Select Fixed/Locked in the Size/State column.
    4. Double-click the Routing Region cell. The Logic Lock Routing Region Settings dialog box appears.
    Figure 18. Logic Lock Region Window
  3. In the Routing Type, specify Fixed with Expansion with Expansion Length of 1.
  4. Click OK.
  5. Click File > Save Project.

    This settings corresponds to the following assignment in the .qsf file: 

    set_instance_assignment -name PLACE_REGION "X1 Y1 X20 Y20" -to <partition hierarchical path>
set_instance_assignment -name RESERVE_PLACE_REGION ON -to <partition hierarchical path>
set_instance_assignment -name CORE_ONLY_PLACE_REGION ON -to <partition hierarchical path>
set_instance_assignment -name REGION_NAME led_inst_0 -to <partition hierarchical path>
set_instance_assignment -name ROUTE_REGION "X0 Y0 X21 Y21" -to <partition hierarchical path>
set_instance_assignment -name RESERVE_ROUTE_REGION OFF -to <partition hierarchical path>
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