Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

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ID 683763
Date 5/24/2022
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Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices 7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations
1.3.1. CvP Limitations x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes 2.3. Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe Wake-Up Time Requirement
4.1.2. PCIe Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel® Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe* Express 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing Open Source CvP Driver in Linux Systems 6.1.5.2. Setting Up the Correct MSEL Switch State 6.1.5.3. Programming CvP Images
6.1.5.1. Installing Open Source CvP Driver in Linux Systems x
6.1.5.1.1. Downstream open source CvP Driver 6.1.5.1.2. Upstream open source CvP Driver
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting Up the Base Revision 6.2.4. Setting Up and Compile the Updated Revision 6.2.5. Converting the SOF File 6.2.6. Programming the Core RBF file from the Updated Revision via PCIe Link
6.2.3. Setting Up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Intel® Agilex™ Devices
7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.05.24 21.4 Removed note about periphery image loading time and configuration from the Power-Up Sequence Timing in CvP Initialization Mode table.
2022.03.02 21.4
  • Updated the CvP System section. The option to enable either lower or upper PCIe Hard block CvP support is enabled in the PCIe Hard IP.
  • Added note for timing sequence i in the Power-Up Sequence Timing in CvP Initialization Mode table.
2021.12.13 21.4 Made the following change:
  • Added conditions used to validate the power-up sequence timing in PCIe* Wake-Up Time Requirement: For CvP Initialization Mode
2021.10.04 21.3 Made the following changes:
  • Revised CvP Support for Intel® Agilex™ Device Family table:
    • Added preliminary tag to the R-tile and F-tile content
    • Added note describing the REFCLK_GXP clock behavior in R-tile
  • Added 100ms PCIe* link up time requirement in CvP Initialization Mode.
  • Updated link for Download the OpenSource Linux CvP Downstream Driver in Generating the Synthesis HDL files for Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe* Express.
  • Added Implementation of CvP Update Mode section and all related subsections.
2021.07.01 21.2
Sections Updated:
  • CvP Modes [CvP Support for Intel Agilex Device Family Table updated
  • Configuration Images [Periphery image and core image definitions updated]
  • CvP Driver Flow [CvP Driver Flow Flowchart updated]
  • Generating the Synthesis HDL files for FPGA P-Tile Avalon Streaming (Avalon-ST) for Express [Enable CVP information added in Step 7]
  • Setting up the CvP Parameters in Device and Pin Options [Step 2b updated]
  • Downstream open source CvP Driver [This is a new section]
  • Upstream open source CvP Driver [This is a new section]
  • Programming CvP Images [Step 7 and Step 8 updated]
2021.03.24 20.4
Sections Updated:
  • CvP Modes
  • CvP System
2020.12.14 20.4 Removed the SDM_IO15 pin documented in Table: CvP Pin Descriptions and Connection Guidelines.
2020.09.15 19.4
  • Added information about the supported tile in Table: CvP Support for Intel® Agilex™ Device Family.
  • Updated following figure and table in section For CvP Initialization Mode:
    • Figure: PCIe Timing Sequence in CvP Initialization Mode
    • Table: Power-Up Sequence Timing in CvP Initialization Mode
2020.01.07 19.4 Initial release.
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