Intel Agilex® 7 Clocking and PLL User Guide: F-Series and I-Series

Download PDF
ID 683761
Date 7/13/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 FPGA F-Series and I-Series Clocking and PLL Overview 2. F-Series and I-Series Clocking and PLL Architecture and Features 3. F-Series and I-Series Clocking and PLL Design Considerations 4. Clock Control Intel® FPGA IP Core 5. IOPLL Intel® FPGA IP Core 6. IOPLL Reconfig Intel® FPGA IP Core 7. Intel Agilex 7 Clocking and PLL User Guide: F-Series and I-Series Archives 8. Document Revision History for the Intel Agilex® 7 Clocking and PLL User Guide: F-Series and I-Series
1. Intel Agilex® 7 FPGA F-Series and I-Series Clocking and PLL Overview x
1.1. Clock Networks Overview 1.2. PLLs Overview
2. F-Series and I-Series Clocking and PLL Architecture and Features x
2.1. Clock Networks Architecture and Features 2.2. PLLs Architecture and Features
2.1. Clock Networks Architecture and Features x
2.1.1. Clock Network Architecture 2.1.2. Clock Resources 2.1.3. Clock Control Features
2.1.1. Clock Network Architecture x
2.1.1.1. Clock Network Hierarchy 2.1.1.2. Clock Sectors 2.1.1.3. Programmable Clock Routing
2.1.3. Clock Control Features x
2.1.3.1. Clock Gating 2.1.3.2. Clock Divider
2.1.3.1. Clock Gating x
2.1.3.1.1. Root Clock Gate 2.1.3.1.2. Sector Clock Gate 2.1.3.1.3. I/O PLL Clock Gate 2.1.3.1.4. LAB Clock Gate
2.2. PLLs Architecture and Features x
2.2.1. PLL Features 2.2.2. PLL Usage 2.2.3. PLL Locations 2.2.4. PLL Architecture 2.2.5. PLL Control Signals 2.2.6. PLL Feedback Modes 2.2.7. Clock Multiplication and Division 2.2.8. Programmable Phase Shift 2.2.9. Programmable Duty Cycle 2.2.10. PLL Cascading 2.2.11. PLL Input Clock Switchover 2.2.12. PLL Reconfiguration and Dynamic Phase Shift 2.2.13. PLL Calibration
2.2.5. PLL Control Signals x
2.2.5.1. Reset 2.2.5.2. Locked
2.2.6. PLL Feedback Modes x
2.2.6.1. Direct Compensation Mode 2.2.6.2. LVDS Compensation Mode 2.2.6.3. Source Synchronous Compensation Mode 2.2.6.4. Normal Compensation Mode 2.2.6.5. Zero-Delay Buffer Mode 2.2.6.6. External Feedback Mode
2.2.11. PLL Input Clock Switchover x
2.2.11.1. Automatic Switchover 2.2.11.2. Automatic Switchover with Manual Override 2.2.11.3. Manual Clock Switchover
2.2.13. PLL Calibration x
2.2.13.1. Power-Up Calibration 2.2.13.2. User Calibration
3. F-Series and I-Series Clocking and PLL Design Considerations x
3.1. Guidelines: Clock Switchover 3.2. Guidelines: Timing Closure 3.3. Guidelines: Resetting the PLL 3.4. Guidelines: Configuration Constraints 3.5. Guidelines: I/O PLL Reconfiguration 3.6. Clocking Constraints 3.7. IP Core Constraints 3.8. Guideline: Achieving 5% Duty Cycle for fOUT_EXT ≥ 300 MHz Using tx_outclk Port from LVDS SERDES Intel® FPGA IP
4. Clock Control Intel® FPGA IP Core x
4.1. Release Information for Clock Control Intel® FPGA IP 4.2. Clock Control IP Core Parameters 4.3. Clock Control IP Core Ports and Signals
5. IOPLL Intel® FPGA IP Core x
5.1. Release Information for IOPLL Intel® FPGA IP 5.2. .mif File Generation 5.3. IP-XACT File Generation 5.4. IOPLL IP Core Parameters 5.5. IOPLL IP Core Ports and Signals
5.2. .mif File Generation x
5.2.1. Generating a New .mif File 5.2.2. Adding Configurations to Existing .mif File
5.3. IP-XACT File Generation x
5.3.1. Generating a New IP-XACT File
5.4. IOPLL IP Core Parameters x
5.4.1. IOPLL IP Core Parameters - PLL Tab 5.4.2. IOPLL IP Core Parameters - Settings Tab 5.4.3. IOPLL IP Core Parameters - Cascading Tab 5.4.4. IOPLL IP Core Parameters - Dynamic Reconfiguration Tab 5.4.5. IOPLL IP Core Parameters - Advanced Parameters Tab
6. IOPLL Reconfig Intel® FPGA IP Core x
6.1. Release Information for IOPLL Reconfig Intel® FPGA IP 6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core 6.3. IOPLL Reconfig IP Core Reconfiguration Modes 6.4. Avalon® Memory-Mapped Interface Ports in the IOPLL Reconfig IP Core 6.5. Address Bus and Data Bus Settings 6.6. Design Example
6.2. Implementing I/O PLL Reconfiguration in the IOPLL Reconfig IP Core x
6.2.1. Connectivity between the IOPLL and IOPLL Reconfig IP Cores 6.2.2. Connecting the IOPLL and IOPLL Reconfig IP Cores
6.3. IOPLL Reconfig IP Core Reconfiguration Modes x
6.3.1. .mif Streaming Reconfiguration 6.3.2. Advanced Mode Reconfiguration 6.3.3. Clock Gating Reconfiguration 6.3.4. Dynamic Phase Shift Reconfiguration
6.3.1. .mif Streaming Reconfiguration x
6.3.1.1. Recalibration Using .mif
6.3.2. Advanced Mode Reconfiguration x
6.3.2.1. Recalibration Using Advanced Mode
6.5. Address Bus and Data Bus Settings x
6.5.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration 6.5.2. Output Clock and the Corresponding Data Bit Setting for Clock Gating Reconfiguration 6.5.3. Data Bus Setting for Dynamic Phase Shift for IOPLL Reconfig IP Core
6.5.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration x
6.5.1.1. Data Bus Setting for Bandwidth Control and Charge Pump 6.5.1.2. Data Bus Setting for Ripplecap
6.6. Design Example x
6.6.1. Reconfiguration Option: .mif Streaming Reconfiguration Using IOPLL Reconfig IP Core 6.6.2. Reconfiguration Option: Advanced Mode Reconfiguration and Recalibration Using IOPLL Reconfig IP Core 6.6.3. Reconfiguration Option: Clock Gating Reconfiguration Using IOPLL Reconfig IP Core
1. Intel Agilex® 7 FPGA F-Series and I-Series Clocking and PLL Overview
2. F-Series and I-Series Clocking and PLL Architecture and Features
3. F-Series and I-Series Clocking and PLL Design Considerations
4. Clock Control Intel® FPGA IP Core
5. IOPLL Intel® FPGA IP Core
6. IOPLL Reconfig Intel® FPGA IP Core
7. Intel Agilex 7 Clocking and PLL User Guide: F-Series and I-Series Archives
8. Document Revision History for the Intel Agilex® 7 Clocking and PLL User Guide: F-Series and I-Series

6.5.1. Address Bus and Data Bus Settings for Advanced Mode Reconfiguration

Table 18.  Address Bus and Data Bus Settings for Advanced Mode Reconfiguration
Register Name Address (Binary) Counter Bit Setting
M Counter High Count 00000100
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00000111
Bypass Enable 15 00000101
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 15 00000110
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
N Counter High Count 00000000
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00000010
Bypass Enable 15 00000001
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 15 00000001
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C1 Counter High Count 00011111
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00100010
Bypass Enable 15 00100000
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 15 00100001
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C2 Counter High Count 00100011
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00100110
Bypass Enable 15 00100100
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 15 00100101
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C3 Counter High Count 00100111
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00101010
Bypass Enable 15 00101000
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 15 00101001
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C4 Counter High Count 00101011
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00101110
Bypass Enable 15 00101100
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 15 00101101
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C5 Counter High Count 00101111
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00110010
Bypass Enable 15 00110000
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 15 00110001
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C6 Counter High Count 00110011
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00110110
Bypass Enable 15 00110100
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 15 00110101
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
C7 Counter High Count 00110111
  • Data[7:0] = high_count
  • Data[7:0] = low_count
  • total_count = high_count + low_count
Low Count 00111010
Bypass Enable 15 00111000
  • Data[0] = bypass enable
    • Data[0] = 1, bypass is enabled. The counter is bypassed with counter division value = 1.
Odd Division 15 00111001
  • Data[7] = Odd division
    • Data[7] = 0, odd division is disabled. The selected counter duty cycle = high_count/total_count.
    • Data[7] = 1, odd division enabled. The selected counter duty cycle = (high_count – 0.5)/total_count.
Charge Pump Current 15 Charge pump setting [2:0] 00000001
  • Data[6:4] = Charge Pump Setting [2:0]
    • Configure charge pump setting [2:0] on data bit 4 to 6.
Charge pump setting [5:3] 00001101
  • Data[7:5] = Charge Pump Setting [5:3]
    • Configure charge pump setting [5:3] on data bit 5 to 7.
Bandwidth Setting 15 — 00001010
  • Data[6:3] = Bandwidth Setting
    • Configure bandwidth setting on data bit 3 to 6.
Ripplecap Setting 15 — 00001010
  • Data[2:1] = Ripplecap Setting
    • Configure ripplecap setting on data bit 1 and 2.
Calibration 15 Calibration Request 01001001
  • Data[6] = Request Calibration
    • Data[6] = 1, to request calibration
Calibration Enable 01001010
  • Data[7:0] = Enable Calibration
    • Data[7:0] = 8’b00000011, to enable calibration

Section Content
Data Bus Setting for Bandwidth Control and Charge Pump
Data Bus Setting for Ripplecap

15 Perform a read-modify-write operation to configure this setting. PLL may lose lock and can cause reliability issue to your device if you configure with the wrong PLL setting, configure the wrong bit, or overwrite the whole byte for settings that made up just part of one byte.
Level Two Title